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@@ -107,13 +107,13 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
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pll_clock->sckcr = of_iomap(node, 0);
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if (pll_clock->sckcr == NULL) {
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pr_err("%s: failed to map divide register", clk_name);
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- goto error;
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+ goto free_clock;
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}
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pll_clock->pllcr = of_iomap(node, 1);
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if (pll_clock->pllcr == NULL) {
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pr_err("%s: failed to map multiply register", clk_name);
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- goto error;
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+ goto unmap_sckcr;
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}
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parent_name = of_clk_get_parent_name(node, 0);
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@@ -125,22 +125,21 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
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pll_clock->hw.init = &init;
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clk = clk_register(NULL, &pll_clock->hw);
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- if (IS_ERR(clk))
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- kfree(pll_clock);
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- if (!IS_ERR(clk)) {
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- of_clk_add_provider(node, of_clk_src_simple_get, clk);
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- return;
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- }
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- pr_err("%s: failed to register %s div clock (%ld)\n",
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- __func__, clk_name, PTR_ERR(clk));
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-error:
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- if (pll_clock) {
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- if (pll_clock->sckcr)
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- iounmap(pll_clock->sckcr);
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- if (pll_clock->pllcr)
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- iounmap(pll_clock->pllcr);
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- kfree(pll_clock);
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+ if (IS_ERR(clk)) {
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+ pr_err("%s: failed to register %s div clock (%ld)\n",
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+ __func__, clk_name, PTR_ERR(clk));
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+ goto unmap_pllcr;
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}
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+
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+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+ return;
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+
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+unmap_pllcr:
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+ iounmap(pll_clock->pllcr);
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+unmap_sckcr:
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+ iounmap(pll_clock->sckcr);
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+free_clock:
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+ kfree(pll_clock);
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}
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CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
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