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@@ -37,6 +37,9 @@
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#include "gmc/gmc_8_1_d.h"
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#include "vi.h"
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+/* Polaris10/11/12 firmware version */
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+#define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
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+
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static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
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static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
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@@ -58,7 +61,9 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
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*/
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static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
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{
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- return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
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+ return ((adev->asic_type >= CHIP_POLARIS10) &&
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+ (adev->asic_type <= CHIP_POLARIS12) &&
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+ (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
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}
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/**
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@@ -411,7 +416,15 @@ static int uvd_v6_0_sw_init(void *handle)
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if (r)
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return r;
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- if (uvd_v6_0_enc_support(adev)) {
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+ if (!uvd_v6_0_enc_support(adev)) {
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+ for (i = 0; i < adev->uvd.num_enc_rings; ++i)
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+ adev->uvd.ring_enc[i].funcs = NULL;
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+
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+ adev->uvd.irq.num_types = 1;
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+ adev->uvd.num_enc_rings = 0;
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+
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+ DRM_INFO("UVD ENC is disabled\n");
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+ } else {
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struct drm_sched_rq *rq;
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ring = &adev->uvd.ring_enc[0];
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rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
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