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+/*
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+ * L2C-310 early resume code. This can be used by platforms to restore
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+ * the settings of their L2 cache controller before restoring the
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+ * processor state.
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+ *
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+ * This code can only be used to if you are running in the secure world.
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+ */
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+#include <linux/linkage.h>
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+#include <asm/hardware/cache-l2x0.h>
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+
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+ .text
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+
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+ENTRY(l2c310_early_resume)
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+ adr r0, 1f
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+ ldr r2, [r0]
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+ add r0, r2, r0
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+
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+ ldmia r0, {r1, r2, r3, r4, r5, r6, r7, r8}
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+ @ r1 = phys address of L2C-310 controller
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+ @ r2 = aux_ctrl
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+ @ r3 = tag_latency
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+ @ r4 = data_latency
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+ @ r5 = filter_start
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+ @ r6 = filter_end
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+ @ r7 = prefetch_ctrl
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+ @ r8 = pwr_ctrl
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+
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+ @ Check that the address has been initialised
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+ teq r1, #0
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+ moveq pc, lr
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+
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+ @ The prefetch and power control registers are revision dependent
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+ @ and can be written whether or not the L2 cache is enabled
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+ ldr r0, [r1, #L2X0_CACHE_ID]
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+ and r0, r0, #L2X0_CACHE_ID_RTL_MASK
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+ cmp r0, #L310_CACHE_ID_RTL_R2P0
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+ strcs r7, [r1, #L310_PREFETCH_CTRL]
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+ cmp r0, #L310_CACHE_ID_RTL_R3P0
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+ strcs r8, [r1, #L310_POWER_CTRL]
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+
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+ @ Don't setup the L2 cache if it is already enabled
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+ ldr r0, [r1, #L2X0_CTRL]
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+ tst r0, #L2X0_CTRL_EN
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+ movne pc, lr
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+
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+ str r3, [r1, #L310_TAG_LATENCY_CTRL]
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+ str r4, [r1, #L310_DATA_LATENCY_CTRL]
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+ str r6, [r1, #L310_ADDR_FILTER_END]
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+ str r5, [r1, #L310_ADDR_FILTER_START]
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+
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+ str r2, [r1, #L2X0_AUX_CTRL]
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+ mov r9, #L2X0_CTRL_EN
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+ str r9, [r1, #L2X0_CTRL]
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+ mov pc, lr
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+ENDPROC(l2c310_early_resume)
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+
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+ .align
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+1: .long l2x0_saved_regs - .
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