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@@ -189,24 +189,36 @@ static void __init sirfsoc_clockevent_init(void)
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}
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}
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/* initialize the kernel jiffy timer source */
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/* initialize the kernel jiffy timer source */
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-static void __init sirfsoc_prima2_timer_init(struct device_node *np)
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+static int __init sirfsoc_prima2_timer_init(struct device_node *np)
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{
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{
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unsigned long rate;
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unsigned long rate;
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struct clk *clk;
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struct clk *clk;
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+ int ret;
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clk = of_clk_get(np, 0);
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clk = of_clk_get(np, 0);
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- BUG_ON(IS_ERR(clk));
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+ if (IS_ERR(clk)) {
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+ pr_err("Failed to get clock");
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+ return PTR_ERR(clk);
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+ }
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- BUG_ON(clk_prepare_enable(clk));
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+ ret = clk_prepare_enable(clk);
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+ if (ret) {
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+ pr_err("Failed to enable clock");
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+ return ret;
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+ }
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rate = clk_get_rate(clk);
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rate = clk_get_rate(clk);
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- BUG_ON(rate < PRIMA2_CLOCK_FREQ);
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- BUG_ON(rate % PRIMA2_CLOCK_FREQ);
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+ if (rate < PRIMA2_CLOCK_FREQ || rate % PRIMA2_CLOCK_FREQ) {
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+ pr_err("Invalid clock rate");
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+ return -EINVAL;
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+ }
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sirfsoc_timer_base = of_iomap(np, 0);
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sirfsoc_timer_base = of_iomap(np, 0);
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- if (!sirfsoc_timer_base)
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- panic("unable to map timer cpu registers\n");
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+ if (!sirfsoc_timer_base) {
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+ pr_err("unable to map timer cpu registers\n");
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+ return -ENXIO;
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+ }
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sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
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sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
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@@ -216,14 +228,23 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np)
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
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writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
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writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
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- BUG_ON(clocksource_register_hz(&sirfsoc_clocksource,
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- PRIMA2_CLOCK_FREQ));
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+ ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
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+ if (ret) {
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+ pr_err("Failed to register clocksource");
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+ return ret;
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+ }
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sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
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sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
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- BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
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+ ret = setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
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+ if (ret) {
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+ pr_err("Failed to setup irq");
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+ return ret;
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+ }
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sirfsoc_clockevent_init();
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sirfsoc_clockevent_init();
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+
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+ return 0;
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}
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}
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-CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer,
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+CLOCKSOURCE_OF_DECLARE_RET(sirfsoc_prima2_timer,
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"sirf,prima2-tick", sirfsoc_prima2_timer_init);
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"sirf,prima2-tick", sirfsoc_prima2_timer_init);
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