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@@ -1060,6 +1060,9 @@ int azx_bus_init(struct azx *chip, const char *model,
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bus->needs_damn_long_delay = 1;
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bus->needs_damn_long_delay = 1;
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}
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}
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+ if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
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+ bus->core.align_bdle_4k = true;
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+
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/* AMD chipsets often cause the communication stalls upon certain
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/* AMD chipsets often cause the communication stalls upon certain
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* sequence like the pin-detection. It seems that forcing the synced
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* sequence like the pin-detection. It seems that forcing the synced
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* access works around the stall. Grrr...
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* access works around the stall. Grrr...
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