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@@ -32,6 +32,7 @@
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#define CPDMA_RXCONTROL 0x14
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#define CPDMA_SOFTRESET 0x1c
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#define CPDMA_RXTEARDOWN 0x18
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+#define CPDMA_TX_PRI0_RATE 0x30
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#define CPDMA_TXINTSTATRAW 0x80
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#define CPDMA_TXINTSTATMASKED 0x84
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#define CPDMA_TXINTMASKSET 0x88
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@@ -68,6 +69,8 @@
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#define CPDMA_TEARDOWN_VALUE 0xfffffffc
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+#define CPDMA_MAX_RLIM_CNT 16384
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+
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struct cpdma_desc {
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/* hardware fields */
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u32 hw_next;
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@@ -122,6 +125,9 @@ struct cpdma_chan {
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struct cpdma_chan_stats stats;
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/* offsets into dmaregs */
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int int_set, int_clear, td;
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+ int weight;
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+ u32 rate_factor;
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+ u32 rate;
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};
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struct cpdma_control_info {
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@@ -134,6 +140,7 @@ struct cpdma_control_info {
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};
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static struct cpdma_control_info controls[] = {
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+ [CPDMA_TX_RLIM] = {CPDMA_DMACONTROL, 8, 0xffff, ACCESS_RW},
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[CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO},
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[CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW},
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[CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW},
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@@ -301,6 +308,186 @@ static int _cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
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return 0;
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}
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+static int _cpdma_control_get(struct cpdma_ctlr *ctlr, int control)
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+{
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+ struct cpdma_control_info *info = &controls[control];
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+ int ret;
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+
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+ if (!ctlr->params.has_ext_regs)
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+ return -ENOTSUPP;
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+
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+ if (ctlr->state != CPDMA_STATE_ACTIVE)
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+ return -EINVAL;
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+
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+ if (control < 0 || control >= ARRAY_SIZE(controls))
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+ return -ENOENT;
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+
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+ if ((info->access & ACCESS_RO) != ACCESS_RO)
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+ return -EPERM;
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+
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+ ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask;
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+ return ret;
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+}
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+
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+/* cpdma_chan_set_chan_shaper - set shaper for a channel
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+ * Has to be called under ctlr lock
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+ */
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+static int cpdma_chan_set_chan_shaper(struct cpdma_chan *chan)
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+{
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+ struct cpdma_ctlr *ctlr = chan->ctlr;
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+ u32 rate_reg;
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+ u32 rmask;
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+ int ret;
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+
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+ if (!chan->rate)
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+ return 0;
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+
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+ rate_reg = CPDMA_TX_PRI0_RATE + 4 * chan->chan_num;
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+ dma_reg_write(ctlr, rate_reg, chan->rate_factor);
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+
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+ rmask = _cpdma_control_get(ctlr, CPDMA_TX_RLIM);
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+ rmask |= chan->mask;
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+
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+ ret = _cpdma_control_set(ctlr, CPDMA_TX_RLIM, rmask);
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+ return ret;
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+}
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+
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+static int cpdma_chan_on(struct cpdma_chan *chan)
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+{
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+ struct cpdma_ctlr *ctlr = chan->ctlr;
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+ struct cpdma_desc_pool *pool = ctlr->pool;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&chan->lock, flags);
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+ if (chan->state != CPDMA_STATE_IDLE) {
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+ spin_unlock_irqrestore(&chan->lock, flags);
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+ return -EBUSY;
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+ }
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+ if (ctlr->state != CPDMA_STATE_ACTIVE) {
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+ spin_unlock_irqrestore(&chan->lock, flags);
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+ return -EINVAL;
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+ }
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+ dma_reg_write(ctlr, chan->int_set, chan->mask);
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+ chan->state = CPDMA_STATE_ACTIVE;
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+ if (chan->head) {
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+ chan_write(chan, hdp, desc_phys(pool, chan->head));
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+ if (chan->rxfree)
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+ chan_write(chan, rxfree, chan->count);
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+ }
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+
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+ spin_unlock_irqrestore(&chan->lock, flags);
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+ return 0;
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+}
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+
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+/* cpdma_chan_fit_rate - set rate for a channel and check if it's possible.
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+ * rmask - mask of rate limited channels
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+ * Returns min rate in Kb/s
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+ */
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+static int cpdma_chan_fit_rate(struct cpdma_chan *ch, u32 rate,
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+ u32 *rmask, int *prio_mode)
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+{
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+ struct cpdma_ctlr *ctlr = ch->ctlr;
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+ struct cpdma_chan *chan;
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+ u32 old_rate = ch->rate;
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+ u32 new_rmask = 0;
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+ int rlim = 1;
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+ int i;
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+
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+ *prio_mode = 0;
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+ for (i = tx_chan_num(0); i < tx_chan_num(CPDMA_MAX_CHANNELS); i++) {
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+ chan = ctlr->channels[i];
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+ if (!chan) {
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+ rlim = 0;
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+ continue;
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+ }
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+
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+ if (chan == ch)
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+ chan->rate = rate;
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+
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+ if (chan->rate) {
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+ if (rlim) {
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+ new_rmask |= chan->mask;
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+ } else {
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+ ch->rate = old_rate;
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+ dev_err(ctlr->dev, "Prev channel of %dch is not rate limited\n",
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+ chan->chan_num);
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+ return -EINVAL;
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+ }
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+ } else {
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+ *prio_mode = 1;
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+ rlim = 0;
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+ }
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+ }
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+
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+ *rmask = new_rmask;
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+ return 0;
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+}
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+
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+static u32 cpdma_chan_set_factors(struct cpdma_ctlr *ctlr,
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+ struct cpdma_chan *ch)
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+{
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+ u32 delta = UINT_MAX, prev_delta = UINT_MAX, best_delta = UINT_MAX;
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+ u32 best_send_cnt = 0, best_idle_cnt = 0;
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+ u32 new_rate, best_rate = 0, rate_reg;
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+ u64 send_cnt, idle_cnt;
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+ u32 min_send_cnt, freq;
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+ u64 divident, divisor;
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+
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+ if (!ch->rate) {
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+ ch->rate_factor = 0;
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+ goto set_factor;
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+ }
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+
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+ freq = ctlr->params.bus_freq_mhz * 1000 * 32;
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+ if (!freq) {
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+ dev_err(ctlr->dev, "The bus frequency is not set\n");
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+ return -EINVAL;
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+ }
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+
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+ min_send_cnt = freq - ch->rate;
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+ send_cnt = DIV_ROUND_UP(min_send_cnt, ch->rate);
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+ while (send_cnt <= CPDMA_MAX_RLIM_CNT) {
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+ divident = ch->rate * send_cnt;
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+ divisor = min_send_cnt;
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+ idle_cnt = DIV_ROUND_CLOSEST_ULL(divident, divisor);
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+
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+ divident = freq * idle_cnt;
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+ divisor = idle_cnt + send_cnt;
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+ new_rate = DIV_ROUND_CLOSEST_ULL(divident, divisor);
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+
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+ delta = new_rate >= ch->rate ? new_rate - ch->rate : delta;
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+ if (delta < best_delta) {
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+ best_delta = delta;
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+ best_send_cnt = send_cnt;
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+ best_idle_cnt = idle_cnt;
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+ best_rate = new_rate;
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+
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+ if (!delta)
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+ break;
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+ }
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+
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+ if (prev_delta >= delta) {
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+ prev_delta = delta;
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+ send_cnt++;
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+ continue;
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+ }
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+
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+ idle_cnt++;
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+ divident = freq * idle_cnt;
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+ send_cnt = DIV_ROUND_CLOSEST_ULL(divident, ch->rate);
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+ send_cnt -= idle_cnt;
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+ prev_delta = UINT_MAX;
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+ }
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+
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+ ch->rate = best_rate;
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+ ch->rate_factor = best_send_cnt | (best_idle_cnt << 16);
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+
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+set_factor:
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+ rate_reg = CPDMA_TX_PRI0_RATE + 4 * ch->chan_num;
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+ dma_reg_write(ctlr, rate_reg, ch->rate_factor);
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+ return 0;
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+}
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+
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struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
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{
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struct cpdma_ctlr *ctlr;
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@@ -331,8 +518,9 @@ EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
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int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
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{
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+ struct cpdma_chan *chan;
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unsigned long flags;
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- int i;
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+ int i, prio_mode;
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spin_lock_irqsave(&ctlr->lock, flags);
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if (ctlr->state != CPDMA_STATE_IDLE) {
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@@ -368,12 +556,20 @@ int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
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ctlr->state = CPDMA_STATE_ACTIVE;
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+ prio_mode = 0;
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for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
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- if (ctlr->channels[i])
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- cpdma_chan_start(ctlr->channels[i]);
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+ chan = ctlr->channels[i];
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+ if (chan) {
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+ cpdma_chan_set_chan_shaper(chan);
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+ cpdma_chan_on(chan);
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+
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+ /* off prio mode if all tx channels are rate limited */
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+ if (is_tx_chan(chan) && !chan->rate)
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+ prio_mode = 1;
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+ }
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}
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- _cpdma_control_set(ctlr, CPDMA_TX_PRIO_FIXED, 1);
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+ _cpdma_control_set(ctlr, CPDMA_TX_PRIO_FIXED, prio_mode);
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_cpdma_control_set(ctlr, CPDMA_RX_BUFFER_OFFSET, 0);
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spin_unlock_irqrestore(&ctlr->lock, flags);
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@@ -474,29 +670,200 @@ u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr)
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}
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EXPORT_SYMBOL_GPL(cpdma_ctrl_txchs_state);
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+static void cpdma_chan_set_descs(struct cpdma_ctlr *ctlr,
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+ int rx, int desc_num,
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+ int per_ch_desc)
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+{
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+ struct cpdma_chan *chan, *most_chan = NULL;
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+ int desc_cnt = desc_num;
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+ int most_dnum = 0;
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+ int min, max, i;
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+
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+ if (!desc_num)
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+ return;
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+
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+ if (rx) {
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+ min = rx_chan_num(0);
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+ max = rx_chan_num(CPDMA_MAX_CHANNELS);
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+ } else {
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+ min = tx_chan_num(0);
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+ max = tx_chan_num(CPDMA_MAX_CHANNELS);
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+ }
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+
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+ for (i = min; i < max; i++) {
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+ chan = ctlr->channels[i];
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+ if (!chan)
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+ continue;
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+
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+ if (chan->weight)
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+ chan->desc_num = (chan->weight * desc_num) / 100;
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+ else
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+ chan->desc_num = per_ch_desc;
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+
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+ desc_cnt -= chan->desc_num;
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+
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+ if (most_dnum < chan->desc_num) {
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+ most_dnum = chan->desc_num;
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+ most_chan = chan;
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+ }
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+ }
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+ /* use remains */
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+ most_chan->desc_num += desc_cnt;
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+}
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+
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/**
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* cpdma_chan_split_pool - Splits ctrl pool between all channels.
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* Has to be called under ctlr lock
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*/
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-static void cpdma_chan_split_pool(struct cpdma_ctlr *ctlr)
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+static int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr)
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{
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+ int tx_per_ch_desc = 0, rx_per_ch_desc = 0;
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struct cpdma_desc_pool *pool = ctlr->pool;
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+ int free_rx_num = 0, free_tx_num = 0;
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+ int rx_weight = 0, tx_weight = 0;
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+ int tx_desc_num, rx_desc_num;
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struct cpdma_chan *chan;
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- int ch_desc_num;
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- int i;
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+ int i, tx_num = 0;
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if (!ctlr->chan_num)
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- return;
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-
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- /* calculate average size of pool slice */
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- ch_desc_num = pool->num_desc / ctlr->chan_num;
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+ return 0;
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- /* split ctlr pool */
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for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
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chan = ctlr->channels[i];
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- if (chan)
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- chan->desc_num = ch_desc_num;
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+ if (!chan)
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+ continue;
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+
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+ if (is_rx_chan(chan)) {
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+ if (!chan->weight)
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+ free_rx_num++;
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+ rx_weight += chan->weight;
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+ } else {
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+ if (!chan->weight)
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+ free_tx_num++;
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+ tx_weight += chan->weight;
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+ tx_num++;
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+ }
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+ }
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+
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+ if (rx_weight > 100 || tx_weight > 100)
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+ return -EINVAL;
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+
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+ tx_desc_num = (tx_num * pool->num_desc) / ctlr->chan_num;
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+ rx_desc_num = pool->num_desc - tx_desc_num;
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+
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+ if (free_tx_num) {
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+ tx_per_ch_desc = tx_desc_num - (tx_weight * tx_desc_num) / 100;
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+ tx_per_ch_desc /= free_tx_num;
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}
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+ if (free_rx_num) {
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+ rx_per_ch_desc = rx_desc_num - (rx_weight * rx_desc_num) / 100;
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+ rx_per_ch_desc /= free_rx_num;
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+ }
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+
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+ cpdma_chan_set_descs(ctlr, 0, tx_desc_num, tx_per_ch_desc);
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+ cpdma_chan_set_descs(ctlr, 1, rx_desc_num, rx_per_ch_desc);
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+
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+ return 0;
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+}
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+
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+/* cpdma_chan_set_weight - set weight of a channel in percentage.
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+ * Tx and Rx channels have separate weights. That is 100% for RX
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+ * and 100% for Tx. The weight is used to split cpdma resources
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+ * in correct proportion required by the channels, including number
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+ * of descriptors. The channel rate is not enough to know the
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+ * weight of a channel as the maximum rate of an interface is needed.
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+ * If weight = 0, then channel uses rest of descriptors leaved by
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+ * weighted channels.
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+ */
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+int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight)
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+{
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+ struct cpdma_ctlr *ctlr = ch->ctlr;
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+ unsigned long flags, ch_flags;
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+ int ret;
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+
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+ spin_lock_irqsave(&ctlr->lock, flags);
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+ spin_lock_irqsave(&ch->lock, ch_flags);
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+ if (ch->weight == weight) {
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+ spin_unlock_irqrestore(&ch->lock, ch_flags);
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+ spin_unlock_irqrestore(&ctlr->lock, flags);
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+ return 0;
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+ }
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+ ch->weight = weight;
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+ spin_unlock_irqrestore(&ch->lock, ch_flags);
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+
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+ /* re-split pool using new channel weight */
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+ ret = cpdma_chan_split_pool(ctlr);
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+ spin_unlock_irqrestore(&ctlr->lock, flags);
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+ return ret;
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+}
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+
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+/* cpdma_chan_get_min_rate - get minimum allowed rate for channel
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+ * Should be called before cpdma_chan_set_rate.
|
|
|
+ * Returns min rate in Kb/s
|
|
|
+ */
|
|
|
+u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr)
|
|
|
+{
|
|
|
+ unsigned int divident, divisor;
|
|
|
+
|
|
|
+ divident = ctlr->params.bus_freq_mhz * 32 * 1000;
|
|
|
+ divisor = 1 + CPDMA_MAX_RLIM_CNT;
|
|
|
+
|
|
|
+ return DIV_ROUND_UP(divident, divisor);
|
|
|
+}
|
|
|
+
|
|
|
+/* cpdma_chan_set_rate - limits bandwidth for transmit channel.
|
|
|
+ * The bandwidth * limited channels have to be in order beginning from lowest.
|
|
|
+ * ch - transmit channel the bandwidth is configured for
|
|
|
+ * rate - bandwidth in Kb/s, if 0 - then off shaper
|
|
|
+ */
|
|
|
+int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate)
|
|
|
+{
|
|
|
+ struct cpdma_ctlr *ctlr = ch->ctlr;
|
|
|
+ unsigned long flags, ch_flags;
|
|
|
+ int ret, prio_mode;
|
|
|
+ u32 rmask;
|
|
|
+
|
|
|
+ if (!ch || !is_tx_chan(ch))
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ if (ch->rate == rate)
|
|
|
+ return rate;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&ctlr->lock, flags);
|
|
|
+ spin_lock_irqsave(&ch->lock, ch_flags);
|
|
|
+
|
|
|
+ ret = cpdma_chan_fit_rate(ch, rate, &rmask, &prio_mode);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ ret = cpdma_chan_set_factors(ctlr, ch);
|
|
|
+ if (ret)
|
|
|
+ goto err;
|
|
|
+
|
|
|
+ spin_unlock_irqrestore(&ch->lock, ch_flags);
|
|
|
+
|
|
|
+ /* on shapers */
|
|
|
+ _cpdma_control_set(ctlr, CPDMA_TX_RLIM, rmask);
|
|
|
+ _cpdma_control_set(ctlr, CPDMA_TX_PRIO_FIXED, prio_mode);
|
|
|
+ spin_unlock_irqrestore(&ctlr->lock, flags);
|
|
|
+ return ret;
|
|
|
+
|
|
|
+err:
|
|
|
+ spin_unlock_irqrestore(&ch->lock, ch_flags);
|
|
|
+ spin_unlock_irqrestore(&ctlr->lock, flags);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+u32 cpdma_chan_get_rate(struct cpdma_chan *ch)
|
|
|
+{
|
|
|
+ unsigned long flags;
|
|
|
+ u32 rate;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&ch->lock, flags);
|
|
|
+ rate = ch->rate;
|
|
|
+ spin_unlock_irqrestore(&ch->lock, flags);
|
|
|
+
|
|
|
+ return rate;
|
|
|
}
|
|
|
|
|
|
struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
|
|
|
@@ -526,7 +893,9 @@ struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
|
|
|
chan->state = CPDMA_STATE_IDLE;
|
|
|
chan->chan_num = chan_num;
|
|
|
chan->handler = handler;
|
|
|
+ chan->rate = 0;
|
|
|
chan->desc_num = ctlr->pool->num_desc / 2;
|
|
|
+ chan->weight = 0;
|
|
|
|
|
|
if (is_rx_chan(chan)) {
|
|
|
chan->hdp = ctlr->params.rxhdp + offset;
|
|
|
@@ -820,28 +1189,20 @@ EXPORT_SYMBOL_GPL(cpdma_chan_process);
|
|
|
|
|
|
int cpdma_chan_start(struct cpdma_chan *chan)
|
|
|
{
|
|
|
- struct cpdma_ctlr *ctlr = chan->ctlr;
|
|
|
- struct cpdma_desc_pool *pool = ctlr->pool;
|
|
|
- unsigned long flags;
|
|
|
+ struct cpdma_ctlr *ctlr = chan->ctlr;
|
|
|
+ unsigned long flags;
|
|
|
+ int ret;
|
|
|
|
|
|
- spin_lock_irqsave(&chan->lock, flags);
|
|
|
- if (chan->state != CPDMA_STATE_IDLE) {
|
|
|
- spin_unlock_irqrestore(&chan->lock, flags);
|
|
|
- return -EBUSY;
|
|
|
- }
|
|
|
- if (ctlr->state != CPDMA_STATE_ACTIVE) {
|
|
|
- spin_unlock_irqrestore(&chan->lock, flags);
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
- dma_reg_write(ctlr, chan->int_set, chan->mask);
|
|
|
- chan->state = CPDMA_STATE_ACTIVE;
|
|
|
- if (chan->head) {
|
|
|
- chan_write(chan, hdp, desc_phys(pool, chan->head));
|
|
|
- if (chan->rxfree)
|
|
|
- chan_write(chan, rxfree, chan->count);
|
|
|
- }
|
|
|
+ spin_lock_irqsave(&ctlr->lock, flags);
|
|
|
+ ret = cpdma_chan_set_chan_shaper(chan);
|
|
|
+ spin_unlock_irqrestore(&ctlr->lock, flags);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = cpdma_chan_on(chan);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
|
|
|
- spin_unlock_irqrestore(&chan->lock, flags);
|
|
|
return 0;
|
|
|
}
|
|
|
EXPORT_SYMBOL_GPL(cpdma_chan_start);
|
|
|
@@ -929,31 +1290,12 @@ int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
|
|
|
int cpdma_control_get(struct cpdma_ctlr *ctlr, int control)
|
|
|
{
|
|
|
unsigned long flags;
|
|
|
- struct cpdma_control_info *info = &controls[control];
|
|
|
int ret;
|
|
|
|
|
|
spin_lock_irqsave(&ctlr->lock, flags);
|
|
|
-
|
|
|
- ret = -ENOTSUPP;
|
|
|
- if (!ctlr->params.has_ext_regs)
|
|
|
- goto unlock_ret;
|
|
|
-
|
|
|
- ret = -EINVAL;
|
|
|
- if (ctlr->state != CPDMA_STATE_ACTIVE)
|
|
|
- goto unlock_ret;
|
|
|
-
|
|
|
- ret = -ENOENT;
|
|
|
- if (control < 0 || control >= ARRAY_SIZE(controls))
|
|
|
- goto unlock_ret;
|
|
|
-
|
|
|
- ret = -EPERM;
|
|
|
- if ((info->access & ACCESS_RO) != ACCESS_RO)
|
|
|
- goto unlock_ret;
|
|
|
-
|
|
|
- ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask;
|
|
|
-
|
|
|
-unlock_ret:
|
|
|
+ ret = _cpdma_control_get(ctlr, control);
|
|
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
|
|
+
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
@@ -965,6 +1307,7 @@ int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
|
|
|
spin_lock_irqsave(&ctlr->lock, flags);
|
|
|
ret = _cpdma_control_set(ctlr, control, value);
|
|
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
|
|
+
|
|
|
return ret;
|
|
|
}
|
|
|
EXPORT_SYMBOL_GPL(cpdma_control_set);
|
David S. Miller