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@@ -0,0 +1,847 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/* Copyright (c) 2018, Intel Corporation. */
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+
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+#include "ice.h"
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+#include "ice_lib.h"
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+
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+/**
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+ * ice_get_vf_vector - get VF interrupt vector register offset
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+ * @vf_msix: number of MSIx vector per VF on a PF
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+ * @vf_id: VF identifier
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+ * @i: index of MSIx vector
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+ */
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+static u32 ice_get_vf_vector(int vf_msix, int vf_id, int i)
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+{
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+ return ((i == 0) ? VFINT_DYN_CTLN(vf_id) :
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+ VFINT_DYN_CTLN(((vf_msix - 1) * (vf_id)) + (i - 1)));
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+}
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+
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+/**
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+ * ice_free_vf_res - Free a VF's resources
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+ * @vf: pointer to the VF info
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+ */
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+static void ice_free_vf_res(struct ice_vf *vf)
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+{
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+ struct ice_pf *pf = vf->pf;
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+ int i, pf_vf_msix;
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+
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+ /* First, disable VF's configuration API to prevent OS from
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+ * accessing the VF's VSI after it's freed or invalidated.
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+ */
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+ clear_bit(ICE_VF_STATE_INIT, vf->vf_states);
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+
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+ /* free vsi & disconnect it from the parent uplink */
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+ if (vf->lan_vsi_idx) {
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+ ice_vsi_release(pf->vsi[vf->lan_vsi_idx]);
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+ vf->lan_vsi_idx = 0;
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+ vf->lan_vsi_num = 0;
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+ vf->num_mac = 0;
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+ }
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+
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+ pf_vf_msix = pf->num_vf_msix;
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+ /* Disable interrupts so that VF starts in a known state */
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+ for (i = 0; i < pf_vf_msix; i++) {
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+ u32 reg_idx;
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+
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+ reg_idx = ice_get_vf_vector(pf_vf_msix, vf->vf_id, i);
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+ wr32(&pf->hw, reg_idx, VFINT_DYN_CTLN_CLEARPBA_M);
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+ ice_flush(&pf->hw);
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+ }
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+ /* reset some of the state variables keeping track of the resources */
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+ clear_bit(ICE_VF_STATE_MC_PROMISC, vf->vf_states);
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+ clear_bit(ICE_VF_STATE_UC_PROMISC, vf->vf_states);
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+}
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+
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+/***********************enable_vf routines*****************************/
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+
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+/**
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+ * ice_dis_vf_mappings
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+ * @vf: pointer to the VF structure
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+ */
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+static void ice_dis_vf_mappings(struct ice_vf *vf)
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+{
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+ struct ice_pf *pf = vf->pf;
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+ struct ice_vsi *vsi;
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+ int first, last, v;
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+ struct ice_hw *hw;
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+
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+ hw = &pf->hw;
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+ vsi = pf->vsi[vf->lan_vsi_idx];
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+
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+ wr32(hw, VPINT_ALLOC(vf->vf_id), 0);
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+
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+ first = vf->first_vector_idx;
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+ last = first + pf->num_vf_msix - 1;
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+ for (v = first; v <= last; v++) {
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+ u32 reg;
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+
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+ reg = (((1 << GLINT_VECT2FUNC_IS_PF_S) &
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+ GLINT_VECT2FUNC_IS_PF_M) |
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+ ((hw->pf_id << GLINT_VECT2FUNC_PF_NUM_S) &
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+ GLINT_VECT2FUNC_PF_NUM_M));
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+ wr32(hw, GLINT_VECT2FUNC(v), reg);
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+ }
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+
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+ if (vsi->tx_mapping_mode == ICE_VSI_MAP_CONTIG)
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+ wr32(hw, VPLAN_TX_QBASE(vf->vf_id), 0);
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+ else
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+ dev_err(&pf->pdev->dev,
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+ "Scattered mode for VF Tx queues is not yet implemented\n");
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+
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+ if (vsi->rx_mapping_mode == ICE_VSI_MAP_CONTIG)
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+ wr32(hw, VPLAN_RX_QBASE(vf->vf_id), 0);
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+ else
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+ dev_err(&pf->pdev->dev,
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+ "Scattered mode for VF Rx queues is not yet implemented\n");
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+}
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+
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+/**
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+ * ice_free_vfs - Free all VFs
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+ * @pf: pointer to the PF structure
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+ */
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+void ice_free_vfs(struct ice_pf *pf)
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+{
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+ struct ice_hw *hw = &pf->hw;
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+ int tmp, i;
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+
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+ if (!pf->vf)
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+ return;
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+
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+ while (test_and_set_bit(__ICE_VF_DIS, pf->state))
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+ usleep_range(1000, 2000);
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+
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+ /* Avoid wait time by stopping all VFs at the same time */
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+ for (i = 0; i < pf->num_alloc_vfs; i++) {
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+ if (!test_bit(ICE_VF_STATE_ENA, pf->vf[i].vf_states))
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+ continue;
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+
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+ /* stop rings without wait time */
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+ ice_vsi_stop_tx_rings(pf->vsi[pf->vf[i].lan_vsi_idx],
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+ ICE_NO_RESET, i);
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+ ice_vsi_stop_rx_rings(pf->vsi[pf->vf[i].lan_vsi_idx]);
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+
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+ clear_bit(ICE_VF_STATE_ENA, pf->vf[i].vf_states);
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+ }
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+
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+ /* Disable IOV before freeing resources. This lets any VF drivers
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+ * running in the host get themselves cleaned up before we yank
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+ * the carpet out from underneath their feet.
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+ */
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+ if (!pci_vfs_assigned(pf->pdev))
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+ pci_disable_sriov(pf->pdev);
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+ else
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+ dev_warn(&pf->pdev->dev, "VFs are assigned - not disabling SR-IOV\n");
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+
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+ tmp = pf->num_alloc_vfs;
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+ pf->num_vf_qps = 0;
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+ pf->num_alloc_vfs = 0;
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+ for (i = 0; i < tmp; i++) {
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+ if (test_bit(ICE_VF_STATE_INIT, pf->vf[i].vf_states)) {
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+ /* disable VF qp mappings */
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+ ice_dis_vf_mappings(&pf->vf[i]);
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+
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+ /* Set this state so that assigned VF vectors can be
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+ * reclaimed by PF for reuse in ice_vsi_release(). No
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+ * need to clear this bit since pf->vf array is being
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+ * freed anyways after this for loop
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+ */
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+ set_bit(ICE_VF_STATE_CFG_INTR, pf->vf[i].vf_states);
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+ ice_free_vf_res(&pf->vf[i]);
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+ }
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+ }
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+
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+ devm_kfree(&pf->pdev->dev, pf->vf);
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+ pf->vf = NULL;
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+
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+ /* This check is for when the driver is unloaded while VFs are
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+ * assigned. Setting the number of VFs to 0 through sysfs is caught
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+ * before this function ever gets called.
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+ */
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+ if (!pci_vfs_assigned(pf->pdev)) {
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+ int vf_id;
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+
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+ /* Acknowledge VFLR for all VFs. Without this, VFs will fail to
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+ * work correctly when SR-IOV gets re-enabled.
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+ */
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+ for (vf_id = 0; vf_id < tmp; vf_id++) {
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+ u32 reg_idx, bit_idx;
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+
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+ reg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;
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+ bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;
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+ wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
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+ }
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+ }
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+ clear_bit(__ICE_VF_DIS, pf->state);
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+ clear_bit(ICE_FLAG_SRIOV_ENA, pf->flags);
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+}
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+
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+/**
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+ * ice_trigger_vf_reset - Reset a VF on HW
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+ * @vf: pointer to the VF structure
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+ * @is_vflr: true if VFLR was issued, false if not
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+ *
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+ * Trigger hardware to start a reset for a particular VF. Expects the caller
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+ * to wait the proper amount of time to allow hardware to reset the VF before
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+ * it cleans up and restores VF functionality.
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+ */
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+static void ice_trigger_vf_reset(struct ice_vf *vf, bool is_vflr)
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+{
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+ struct ice_pf *pf = vf->pf;
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+ u32 reg, reg_idx, bit_idx;
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+ struct ice_hw *hw;
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+ int vf_abs_id, i;
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+
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+ hw = &pf->hw;
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+ vf_abs_id = vf->vf_id + hw->func_caps.vf_base_id;
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+
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+ /* Inform VF that it is no longer active, as a warning */
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+ clear_bit(ICE_VF_STATE_ACTIVE, vf->vf_states);
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+
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+ /* Disable VF's configuration API during reset. The flag is re-enabled
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+ * in ice_alloc_vf_res(), when it's safe again to access VF's VSI.
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+ * It's normally disabled in ice_free_vf_res(), but it's safer
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+ * to do it earlier to give some time to finish to any VF config
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+ * functions that may still be running at this point.
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+ */
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+ clear_bit(ICE_VF_STATE_INIT, vf->vf_states);
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+
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+ /* In the case of a VFLR, the HW has already reset the VF and we
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+ * just need to clean up, so don't hit the VFRTRIG register.
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+ */
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+ if (!is_vflr) {
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+ /* reset VF using VPGEN_VFRTRIG reg */
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+ reg = rd32(hw, VPGEN_VFRTRIG(vf->vf_id));
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+ reg |= VPGEN_VFRTRIG_VFSWR_M;
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+ wr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg);
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+ }
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+ /* clear the VFLR bit in GLGEN_VFLRSTAT */
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+ reg_idx = (vf_abs_id) / 32;
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+ bit_idx = (vf_abs_id) % 32;
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+ wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
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+ ice_flush(hw);
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+
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+ wr32(hw, PF_PCI_CIAA,
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+ VF_DEVICE_STATUS | (vf_abs_id << PF_PCI_CIAA_VF_NUM_S));
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+ for (i = 0; i < 100; i++) {
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+ reg = rd32(hw, PF_PCI_CIAD);
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+ if ((reg & VF_TRANS_PENDING_M) != 0)
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+ dev_err(&pf->pdev->dev,
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+ "VF %d PCI transactions stuck\n", vf->vf_id);
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+ udelay(1);
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+ }
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+}
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+
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+/**
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+ * ice_vsi_set_pvid - Set port VLAN id for the VSI
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+ * @vsi: the VSI being changed
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+ * @vid: the VLAN id to set as a PVID
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+ */
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+static int ice_vsi_set_pvid(struct ice_vsi *vsi, u16 vid)
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+{
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+ struct device *dev = &vsi->back->pdev->dev;
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+ struct ice_hw *hw = &vsi->back->hw;
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+ struct ice_vsi_ctx ctxt = { 0 };
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+ enum ice_status status;
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+
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+ ctxt.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_TAGGED |
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+ ICE_AQ_VSI_PVLAN_INSERT_PVID |
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+ ICE_AQ_VSI_VLAN_EMOD_STR;
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+ ctxt.info.pvid = cpu_to_le16(vid);
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+ ctxt.info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);
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+
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+ status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
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+ if (status) {
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+ dev_info(dev, "update VSI for VLAN insert failed, err %d aq_err %d\n",
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+ status, hw->adminq.sq_last_status);
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+ return -EIO;
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+ }
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+
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+ vsi->info.pvid = ctxt.info.pvid;
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+ vsi->info.vlan_flags = ctxt.info.vlan_flags;
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+ return 0;
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+}
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+
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+/**
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+ * ice_vf_vsi_setup - Set up a VF VSI
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+ * @pf: board private structure
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+ * @pi: pointer to the port_info instance
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+ * @vf_id: defines VF id to which this VSI connects.
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+ *
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+ * Returns pointer to the successfully allocated VSI struct on success,
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+ * otherwise returns NULL on failure.
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+ */
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+static struct ice_vsi *
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+ice_vf_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi, u16 vf_id)
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+{
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+ return ice_vsi_setup(pf, pi, ICE_VSI_VF, vf_id);
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+}
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+
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+/**
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+ * ice_alloc_vsi_res - Setup VF VSI and its resources
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+ * @vf: pointer to the VF structure
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+ *
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+ * Returns 0 on success, negative value on failure
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+ */
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+static int ice_alloc_vsi_res(struct ice_vf *vf)
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+{
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+ struct ice_pf *pf = vf->pf;
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+ LIST_HEAD(tmp_add_list);
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+ u8 broadcast[ETH_ALEN];
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+ struct ice_vsi *vsi;
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+ int status = 0;
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+
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+ vsi = ice_vf_vsi_setup(pf, pf->hw.port_info, vf->vf_id);
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+
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+ if (!vsi) {
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+ dev_err(&pf->pdev->dev, "Failed to create VF VSI\n");
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+ return -ENOMEM;
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+ }
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+
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+ vf->lan_vsi_idx = vsi->idx;
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+ vf->lan_vsi_num = vsi->vsi_num;
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+
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+ /* first vector index is the VFs OICR index */
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+ vf->first_vector_idx = vsi->hw_base_vector;
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+ /* Since hw_base_vector holds the vector where data queue interrupts
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+ * starts, increment by 1 since VFs allocated vectors include OICR intr
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+ * as well.
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+ */
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+ vsi->hw_base_vector += 1;
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+
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+ /* Check if port VLAN exist before, and restore it accordingly */
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+ if (vf->port_vlan_id)
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+ ice_vsi_set_pvid(vsi, vf->port_vlan_id);
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+
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+ eth_broadcast_addr(broadcast);
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+
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+ status = ice_add_mac_to_list(vsi, &tmp_add_list, broadcast);
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+ if (status)
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+ goto ice_alloc_vsi_res_exit;
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+
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+ if (is_valid_ether_addr(vf->dflt_lan_addr.addr)) {
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+ status = ice_add_mac_to_list(vsi, &tmp_add_list,
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+ vf->dflt_lan_addr.addr);
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+ if (status)
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+ goto ice_alloc_vsi_res_exit;
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+ }
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+
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+ status = ice_add_mac(&pf->hw, &tmp_add_list);
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+ if (status)
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+ dev_err(&pf->pdev->dev, "could not add mac filters\n");
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+
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+ /* Clear this bit after VF initialization since we shouldn't reclaim
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+ * and reassign interrupts for synchronous or asynchronous VFR events.
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+ * We don't want to reconfigure interrupts since AVF driver doesn't
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+ * expect vector assignment to be changed unless there is a request for
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+ * more vectors.
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+ */
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+ clear_bit(ICE_VF_STATE_CFG_INTR, vf->vf_states);
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+ice_alloc_vsi_res_exit:
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+ ice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);
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+ return status;
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+}
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+
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+/**
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+ * ice_alloc_vf_res - Allocate VF resources
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+ * @vf: pointer to the VF structure
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+ */
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+static int ice_alloc_vf_res(struct ice_vf *vf)
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+{
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+ int status;
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+
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+ /* setup VF VSI and necessary resources */
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+ status = ice_alloc_vsi_res(vf);
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+ if (status)
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+ goto ice_alloc_vf_res_exit;
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+
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+ if (vf->trusted)
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+ set_bit(ICE_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);
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+ else
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+ clear_bit(ICE_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);
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+
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+ /* VF is now completely initialized */
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+ set_bit(ICE_VF_STATE_INIT, vf->vf_states);
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+
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+ return status;
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+
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+ice_alloc_vf_res_exit:
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+ ice_free_vf_res(vf);
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+ return status;
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+}
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+
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+/**
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|
|
+ * ice_ena_vf_mappings
|
|
|
+ * @vf: pointer to the VF structure
|
|
|
+ *
|
|
|
+ * Enable VF vectors and queues allocation by writing the details into
|
|
|
+ * respective registers.
|
|
|
+ */
|
|
|
+static void ice_ena_vf_mappings(struct ice_vf *vf)
|
|
|
+{
|
|
|
+ struct ice_pf *pf = vf->pf;
|
|
|
+ struct ice_vsi *vsi;
|
|
|
+ int first, last, v;
|
|
|
+ struct ice_hw *hw;
|
|
|
+ int abs_vf_id;
|
|
|
+ u32 reg;
|
|
|
+
|
|
|
+ hw = &pf->hw;
|
|
|
+ vsi = pf->vsi[vf->lan_vsi_idx];
|
|
|
+ first = vf->first_vector_idx;
|
|
|
+ last = (first + pf->num_vf_msix) - 1;
|
|
|
+ abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
|
|
|
+
|
|
|
+ /* VF Vector allocation */
|
|
|
+ reg = (((first << VPINT_ALLOC_FIRST_S) & VPINT_ALLOC_FIRST_M) |
|
|
|
+ ((last << VPINT_ALLOC_LAST_S) & VPINT_ALLOC_LAST_M) |
|
|
|
+ VPINT_ALLOC_VALID_M);
|
|
|
+ wr32(hw, VPINT_ALLOC(vf->vf_id), reg);
|
|
|
+
|
|
|
+ /* map the interrupts to its functions */
|
|
|
+ for (v = first; v <= last; v++) {
|
|
|
+ reg = (((abs_vf_id << GLINT_VECT2FUNC_VF_NUM_S) &
|
|
|
+ GLINT_VECT2FUNC_VF_NUM_M) |
|
|
|
+ ((hw->pf_id << GLINT_VECT2FUNC_PF_NUM_S) &
|
|
|
+ GLINT_VECT2FUNC_PF_NUM_M));
|
|
|
+ wr32(hw, GLINT_VECT2FUNC(v), reg);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* VF Tx queues allocation */
|
|
|
+ if (vsi->tx_mapping_mode == ICE_VSI_MAP_CONTIG) {
|
|
|
+ wr32(hw, VPLAN_TXQ_MAPENA(vf->vf_id),
|
|
|
+ VPLAN_TXQ_MAPENA_TX_ENA_M);
|
|
|
+ /* set the VF PF Tx queue range
|
|
|
+ * VFNUMQ value should be set to (number of queues - 1). A value
|
|
|
+ * of 0 means 1 queue and a value of 255 means 256 queues
|
|
|
+ */
|
|
|
+ reg = (((vsi->txq_map[0] << VPLAN_TX_QBASE_VFFIRSTQ_S) &
|
|
|
+ VPLAN_TX_QBASE_VFFIRSTQ_M) |
|
|
|
+ (((vsi->alloc_txq - 1) << VPLAN_TX_QBASE_VFNUMQ_S) &
|
|
|
+ VPLAN_TX_QBASE_VFNUMQ_M));
|
|
|
+ wr32(hw, VPLAN_TX_QBASE(vf->vf_id), reg);
|
|
|
+ } else {
|
|
|
+ dev_err(&pf->pdev->dev,
|
|
|
+ "Scattered mode for VF Tx queues is not yet implemented\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ /* VF Rx queues allocation */
|
|
|
+ if (vsi->rx_mapping_mode == ICE_VSI_MAP_CONTIG) {
|
|
|
+ wr32(hw, VPLAN_RXQ_MAPENA(vf->vf_id),
|
|
|
+ VPLAN_RXQ_MAPENA_RX_ENA_M);
|
|
|
+ /* set the VF PF Rx queue range
|
|
|
+ * VFNUMQ value should be set to (number of queues - 1). A value
|
|
|
+ * of 0 means 1 queue and a value of 255 means 256 queues
|
|
|
+ */
|
|
|
+ reg = (((vsi->rxq_map[0] << VPLAN_RX_QBASE_VFFIRSTQ_S) &
|
|
|
+ VPLAN_RX_QBASE_VFFIRSTQ_M) |
|
|
|
+ (((vsi->alloc_txq - 1) << VPLAN_RX_QBASE_VFNUMQ_S) &
|
|
|
+ VPLAN_RX_QBASE_VFNUMQ_M));
|
|
|
+ wr32(hw, VPLAN_RX_QBASE(vf->vf_id), reg);
|
|
|
+ } else {
|
|
|
+ dev_err(&pf->pdev->dev,
|
|
|
+ "Scattered mode for VF Rx queues is not yet implemented\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ice_determine_res
|
|
|
+ * @pf: pointer to the PF structure
|
|
|
+ * @avail_res: available resources in the PF structure
|
|
|
+ * @max_res: maximum resources that can be given per VF
|
|
|
+ * @min_res: minimum resources that can be given per VF
|
|
|
+ *
|
|
|
+ * Returns non-zero value if resources (queues/vectors) are available or
|
|
|
+ * returns zero if PF cannot accommodate for all num_alloc_vfs.
|
|
|
+ */
|
|
|
+static int
|
|
|
+ice_determine_res(struct ice_pf *pf, u16 avail_res, u16 max_res, u16 min_res)
|
|
|
+{
|
|
|
+ bool checked_min_res = false;
|
|
|
+ int res;
|
|
|
+
|
|
|
+ /* start by checking if PF can assign max number of resources for
|
|
|
+ * all num_alloc_vfs.
|
|
|
+ * if yes, return number per VF
|
|
|
+ * If no, divide by 2 and roundup, check again
|
|
|
+ * repeat the loop till we reach a point where even minimum resources
|
|
|
+ * are not available, in that case return 0
|
|
|
+ */
|
|
|
+ res = max_res;
|
|
|
+ while ((res >= min_res) && !checked_min_res) {
|
|
|
+ int num_all_res;
|
|
|
+
|
|
|
+ num_all_res = pf->num_alloc_vfs * res;
|
|
|
+ if (num_all_res <= avail_res)
|
|
|
+ return res;
|
|
|
+
|
|
|
+ if (res == min_res)
|
|
|
+ checked_min_res = true;
|
|
|
+
|
|
|
+ res = DIV_ROUND_UP(res, 2);
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ice_check_avail_res - check if vectors and queues are available
|
|
|
+ * @pf: pointer to the PF structure
|
|
|
+ *
|
|
|
+ * This function is where we calculate actual number of resources for VF VSIs,
|
|
|
+ * we don't reserve ahead of time during probe. Returns success if vectors and
|
|
|
+ * queues resources are available, otherwise returns error code
|
|
|
+ */
|
|
|
+static int ice_check_avail_res(struct ice_pf *pf)
|
|
|
+{
|
|
|
+ u16 num_msix, num_txq, num_rxq;
|
|
|
+
|
|
|
+ if (!pf->num_alloc_vfs)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ /* Grab from HW interrupts common pool
|
|
|
+ * Note: By the time the user decides it needs more vectors in a VF
|
|
|
+ * its already too late since one must decide this prior to creating the
|
|
|
+ * VF interface. So the best we can do is take a guess as to what the
|
|
|
+ * user might want.
|
|
|
+ *
|
|
|
+ * We have two policies for vector allocation:
|
|
|
+ * 1. if num_alloc_vfs is from 1 to 16, then we consider this as small
|
|
|
+ * number of NFV VFs used for NFV appliances, since this is a special
|
|
|
+ * case, we try to assign maximum vectors per VF (65) as much as
|
|
|
+ * possible, based on determine_resources algorithm.
|
|
|
+ * 2. if num_alloc_vfs is from 17 to 256, then its large number of
|
|
|
+ * regular VFs which are not used for any special purpose. Hence try to
|
|
|
+ * grab default interrupt vectors (5 as supported by AVF driver).
|
|
|
+ */
|
|
|
+ if (pf->num_alloc_vfs <= 16) {
|
|
|
+ num_msix = ice_determine_res(pf, pf->num_avail_hw_msix,
|
|
|
+ ICE_MAX_INTR_PER_VF,
|
|
|
+ ICE_MIN_INTR_PER_VF);
|
|
|
+ } else if (pf->num_alloc_vfs <= ICE_MAX_VF_COUNT) {
|
|
|
+ num_msix = ice_determine_res(pf, pf->num_avail_hw_msix,
|
|
|
+ ICE_DFLT_INTR_PER_VF,
|
|
|
+ ICE_MIN_INTR_PER_VF);
|
|
|
+ } else {
|
|
|
+ dev_err(&pf->pdev->dev,
|
|
|
+ "Number of VFs %d exceeds max VF count %d\n",
|
|
|
+ pf->num_alloc_vfs, ICE_MAX_VF_COUNT);
|
|
|
+ return -EIO;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!num_msix)
|
|
|
+ return -EIO;
|
|
|
+
|
|
|
+ /* Grab from the common pool
|
|
|
+ * start by requesting Default queues (4 as supported by AVF driver),
|
|
|
+ * Note that, the main difference between queues and vectors is, latter
|
|
|
+ * can only be reserved at init time but queues can be requested by VF
|
|
|
+ * at runtime through Virtchnl, that is the reason we start by reserving
|
|
|
+ * few queues.
|
|
|
+ */
|
|
|
+ num_txq = ice_determine_res(pf, pf->q_left_tx, ICE_DFLT_QS_PER_VF,
|
|
|
+ ICE_MIN_QS_PER_VF);
|
|
|
+
|
|
|
+ num_rxq = ice_determine_res(pf, pf->q_left_rx, ICE_DFLT_QS_PER_VF,
|
|
|
+ ICE_MIN_QS_PER_VF);
|
|
|
+
|
|
|
+ if (!num_txq || !num_rxq)
|
|
|
+ return -EIO;
|
|
|
+
|
|
|
+ /* since AVF driver works with only queue pairs which means, it expects
|
|
|
+ * to have equal number of Rx and Tx queues, so take the minimum of
|
|
|
+ * available Tx or Rx queues
|
|
|
+ */
|
|
|
+ pf->num_vf_qps = min_t(int, num_txq, num_rxq);
|
|
|
+ pf->num_vf_msix = num_msix;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ice_cleanup_and_realloc_vf - Clean up VF and reallocate resources after reset
|
|
|
+ * @vf: pointer to the VF structure
|
|
|
+ *
|
|
|
+ * Cleanup a VF after the hardware reset is finished. Expects the caller to
|
|
|
+ * have verified whether the reset is finished properly, and ensure the
|
|
|
+ * minimum amount of wait time has passed. Reallocate VF resources back to make
|
|
|
+ * VF state active
|
|
|
+ */
|
|
|
+static void ice_cleanup_and_realloc_vf(struct ice_vf *vf)
|
|
|
+{
|
|
|
+ struct ice_pf *pf = vf->pf;
|
|
|
+ struct ice_hw *hw;
|
|
|
+ u32 reg;
|
|
|
+
|
|
|
+ hw = &pf->hw;
|
|
|
+
|
|
|
+ /* PF software completes the flow by notifying VF that reset flow is
|
|
|
+ * completed. This is done by enabling hardware by clearing the reset
|
|
|
+ * bit in the VPGEN_VFRTRIG reg and setting VFR_STATE in the VFGEN_RSTAT
|
|
|
+ * register to VFR completed (done at the end of this function)
|
|
|
+ * By doing this we allow HW to access VF memory at any point. If we
|
|
|
+ * did it any sooner, HW could access memory while it was being freed
|
|
|
+ * in ice_free_vf_res(), causing an IOMMU fault.
|
|
|
+ *
|
|
|
+ * On the other hand, this needs to be done ASAP, because the VF driver
|
|
|
+ * is waiting for this to happen and may report a timeout. It's
|
|
|
+ * harmless, but it gets logged into Guest OS kernel log, so best avoid
|
|
|
+ * it.
|
|
|
+ */
|
|
|
+ reg = rd32(hw, VPGEN_VFRTRIG(vf->vf_id));
|
|
|
+ reg &= ~VPGEN_VFRTRIG_VFSWR_M;
|
|
|
+ wr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg);
|
|
|
+
|
|
|
+ /* reallocate VF resources to finish resetting the VSI state */
|
|
|
+ if (!ice_alloc_vf_res(vf)) {
|
|
|
+ ice_ena_vf_mappings(vf);
|
|
|
+ set_bit(ICE_VF_STATE_ACTIVE, vf->vf_states);
|
|
|
+ clear_bit(ICE_VF_STATE_DIS, vf->vf_states);
|
|
|
+ vf->num_vlan = 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Tell the VF driver the reset is done. This needs to be done only
|
|
|
+ * after VF has been fully initialized, because the VF driver may
|
|
|
+ * request resources immediately after setting this flag.
|
|
|
+ */
|
|
|
+ wr32(hw, VFGEN_RSTAT(vf->vf_id), VIRTCHNL_VFR_VFACTIVE);
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ice_reset_all_vfs - reset all allocated VFs in one go
|
|
|
+ * @pf: pointer to the PF structure
|
|
|
+ * @is_vflr: true if VFLR was issued, false if not
|
|
|
+ *
|
|
|
+ * First, tell the hardware to reset each VF, then do all the waiting in one
|
|
|
+ * chunk, and finally finish restoring each VF after the wait. This is useful
|
|
|
+ * during PF routines which need to reset all VFs, as otherwise it must perform
|
|
|
+ * these resets in a serialized fashion.
|
|
|
+ *
|
|
|
+ * Returns true if any VFs were reset, and false otherwise.
|
|
|
+ */
|
|
|
+bool ice_reset_all_vfs(struct ice_pf *pf, bool is_vflr)
|
|
|
+{
|
|
|
+ struct ice_hw *hw = &pf->hw;
|
|
|
+ int v, i;
|
|
|
+
|
|
|
+ /* If we don't have any VFs, then there is nothing to reset */
|
|
|
+ if (!pf->num_alloc_vfs)
|
|
|
+ return false;
|
|
|
+
|
|
|
+ /* If VFs have been disabled, there is no need to reset */
|
|
|
+ if (test_and_set_bit(__ICE_VF_DIS, pf->state))
|
|
|
+ return false;
|
|
|
+
|
|
|
+ /* Begin reset on all VFs at once */
|
|
|
+ for (v = 0; v < pf->num_alloc_vfs; v++)
|
|
|
+ ice_trigger_vf_reset(&pf->vf[v], is_vflr);
|
|
|
+
|
|
|
+ /* Call Disable LAN Tx queue AQ call with VFR bit set and 0
|
|
|
+ * queues to inform Firmware about VF reset.
|
|
|
+ */
|
|
|
+ for (v = 0; v < pf->num_alloc_vfs; v++)
|
|
|
+ ice_dis_vsi_txq(pf->vsi[0]->port_info, 0, NULL, NULL,
|
|
|
+ ICE_VF_RESET, v, NULL);
|
|
|
+
|
|
|
+ /* HW requires some time to make sure it can flush the FIFO for a VF
|
|
|
+ * when it resets it. Poll the VPGEN_VFRSTAT register for each VF in
|
|
|
+ * sequence to make sure that it has completed. We'll keep track of
|
|
|
+ * the VFs using a simple iterator that increments once that VF has
|
|
|
+ * finished resetting.
|
|
|
+ */
|
|
|
+ for (i = 0, v = 0; i < 10 && v < pf->num_alloc_vfs; i++) {
|
|
|
+ usleep_range(10000, 20000);
|
|
|
+
|
|
|
+ /* Check each VF in sequence */
|
|
|
+ while (v < pf->num_alloc_vfs) {
|
|
|
+ struct ice_vf *vf = &pf->vf[v];
|
|
|
+ u32 reg;
|
|
|
+
|
|
|
+ reg = rd32(hw, VPGEN_VFRSTAT(vf->vf_id));
|
|
|
+ if (!(reg & VPGEN_VFRSTAT_VFRD_M))
|
|
|
+ break;
|
|
|
+
|
|
|
+ /* If the current VF has finished resetting, move on
|
|
|
+ * to the next VF in sequence.
|
|
|
+ */
|
|
|
+ v++;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Display a warning if at least one VF didn't manage to reset in
|
|
|
+ * time, but continue on with the operation.
|
|
|
+ */
|
|
|
+ if (v < pf->num_alloc_vfs)
|
|
|
+ dev_warn(&pf->pdev->dev, "VF reset check timeout\n");
|
|
|
+ usleep_range(10000, 20000);
|
|
|
+
|
|
|
+ /* free VF resources to begin resetting the VSI state */
|
|
|
+ for (v = 0; v < pf->num_alloc_vfs; v++)
|
|
|
+ ice_free_vf_res(&pf->vf[v]);
|
|
|
+
|
|
|
+ if (ice_check_avail_res(pf)) {
|
|
|
+ dev_err(&pf->pdev->dev,
|
|
|
+ "Cannot allocate VF resources, try with fewer number of VFs\n");
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Finish the reset on each VF */
|
|
|
+ for (v = 0; v < pf->num_alloc_vfs; v++)
|
|
|
+ ice_cleanup_and_realloc_vf(&pf->vf[v]);
|
|
|
+
|
|
|
+ ice_flush(hw);
|
|
|
+ clear_bit(__ICE_VF_DIS, pf->state);
|
|
|
+
|
|
|
+ return true;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ice_alloc_vfs - Allocate and set up VFs resources
|
|
|
+ * @pf: pointer to the PF structure
|
|
|
+ * @num_alloc_vfs: number of VFs to allocate
|
|
|
+ */
|
|
|
+static int ice_alloc_vfs(struct ice_pf *pf, u16 num_alloc_vfs)
|
|
|
+{
|
|
|
+ struct ice_hw *hw = &pf->hw;
|
|
|
+ struct ice_vf *vfs;
|
|
|
+ int i, ret;
|
|
|
+
|
|
|
+ /* Disable global interrupt 0 so we don't try to handle the VFLR. */
|
|
|
+ wr32(hw, GLINT_DYN_CTL(pf->hw_oicr_idx),
|
|
|
+ ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S);
|
|
|
+
|
|
|
+ ice_flush(hw);
|
|
|
+
|
|
|
+ ret = pci_enable_sriov(pf->pdev, num_alloc_vfs);
|
|
|
+ if (ret) {
|
|
|
+ pf->num_alloc_vfs = 0;
|
|
|
+ goto err_unroll_intr;
|
|
|
+ }
|
|
|
+ /* allocate memory */
|
|
|
+ vfs = devm_kcalloc(&pf->pdev->dev, num_alloc_vfs, sizeof(*vfs),
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!vfs) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto err_unroll_sriov;
|
|
|
+ }
|
|
|
+ pf->vf = vfs;
|
|
|
+
|
|
|
+ /* apply default profile */
|
|
|
+ for (i = 0; i < num_alloc_vfs; i++) {
|
|
|
+ vfs[i].pf = pf;
|
|
|
+ vfs[i].vf_sw_id = pf->first_sw;
|
|
|
+ vfs[i].vf_id = i;
|
|
|
+
|
|
|
+ /* assign default capabilities */
|
|
|
+ set_bit(ICE_VIRTCHNL_VF_CAP_L2, &vfs[i].vf_caps);
|
|
|
+ vfs[i].spoofchk = true;
|
|
|
+
|
|
|
+ /* Set this state so that PF driver does VF vector assignment */
|
|
|
+ set_bit(ICE_VF_STATE_CFG_INTR, vfs[i].vf_states);
|
|
|
+ }
|
|
|
+ pf->num_alloc_vfs = num_alloc_vfs;
|
|
|
+
|
|
|
+ /* VF resources get allocated during reset */
|
|
|
+ if (!ice_reset_all_vfs(pf, false))
|
|
|
+ goto err_unroll_sriov;
|
|
|
+
|
|
|
+ goto err_unroll_intr;
|
|
|
+
|
|
|
+err_unroll_sriov:
|
|
|
+ pci_disable_sriov(pf->pdev);
|
|
|
+err_unroll_intr:
|
|
|
+ /* rearm interrupts here */
|
|
|
+ ice_irq_dynamic_ena(hw, NULL, NULL);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ice_pf_state_is_nominal - checks the pf for nominal state
|
|
|
+ * @pf: pointer to pf to check
|
|
|
+ *
|
|
|
+ * Check the PF's state for a collection of bits that would indicate
|
|
|
+ * the PF is in a state that would inhibit normal operation for
|
|
|
+ * driver functionality.
|
|
|
+ *
|
|
|
+ * Returns true if PF is in a nominal state.
|
|
|
+ * Returns false otherwise
|
|
|
+ */
|
|
|
+static bool ice_pf_state_is_nominal(struct ice_pf *pf)
|
|
|
+{
|
|
|
+ DECLARE_BITMAP(check_bits, __ICE_STATE_NBITS) = { 0 };
|
|
|
+
|
|
|
+ if (!pf)
|
|
|
+ return false;
|
|
|
+
|
|
|
+ bitmap_set(check_bits, 0, __ICE_STATE_NOMINAL_CHECK_BITS);
|
|
|
+ if (bitmap_intersects(pf->state, check_bits, __ICE_STATE_NBITS))
|
|
|
+ return false;
|
|
|
+
|
|
|
+ return true;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ice_pci_sriov_ena - Enable or change number of VFs
|
|
|
+ * @pf: pointer to the PF structure
|
|
|
+ * @num_vfs: number of VFs to allocate
|
|
|
+ */
|
|
|
+static int ice_pci_sriov_ena(struct ice_pf *pf, int num_vfs)
|
|
|
+{
|
|
|
+ int pre_existing_vfs = pci_num_vf(pf->pdev);
|
|
|
+ struct device *dev = &pf->pdev->dev;
|
|
|
+ int err;
|
|
|
+
|
|
|
+ if (!ice_pf_state_is_nominal(pf)) {
|
|
|
+ dev_err(dev, "Cannot enable SR-IOV, device not ready\n");
|
|
|
+ return -EBUSY;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!test_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags)) {
|
|
|
+ dev_err(dev, "This device is not capable of SR-IOV\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (pre_existing_vfs && pre_existing_vfs != num_vfs)
|
|
|
+ ice_free_vfs(pf);
|
|
|
+ else if (pre_existing_vfs && pre_existing_vfs == num_vfs)
|
|
|
+ return num_vfs;
|
|
|
+
|
|
|
+ if (num_vfs > pf->num_vfs_supported) {
|
|
|
+ dev_err(dev, "Can't enable %d VFs, max VFs supported is %d\n",
|
|
|
+ num_vfs, pf->num_vfs_supported);
|
|
|
+ return -ENOTSUPP;
|
|
|
+ }
|
|
|
+
|
|
|
+ dev_info(dev, "Allocating %d VFs\n", num_vfs);
|
|
|
+ err = ice_alloc_vfs(pf, num_vfs);
|
|
|
+ if (err) {
|
|
|
+ dev_err(dev, "Failed to enable SR-IOV: %d\n", err);
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ set_bit(ICE_FLAG_SRIOV_ENA, pf->flags);
|
|
|
+ return num_vfs;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ice_sriov_configure - Enable or change number of VFs via sysfs
|
|
|
+ * @pdev: pointer to a pci_dev structure
|
|
|
+ * @num_vfs: number of VFs to allocate
|
|
|
+ *
|
|
|
+ * This function is called when the user updates the number of VFs in sysfs.
|
|
|
+ */
|
|
|
+int ice_sriov_configure(struct pci_dev *pdev, int num_vfs)
|
|
|
+{
|
|
|
+ struct ice_pf *pf = pci_get_drvdata(pdev);
|
|
|
+
|
|
|
+ if (num_vfs)
|
|
|
+ return ice_pci_sriov_ena(pf, num_vfs);
|
|
|
+
|
|
|
+ if (!pci_vfs_assigned(pdev)) {
|
|
|
+ ice_free_vfs(pf);
|
|
|
+ } else {
|
|
|
+ dev_err(&pf->pdev->dev,
|
|
|
+ "can't free VFs because some are assigned to VMs.\n");
|
|
|
+ return -EBUSY;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
Anirudh Venkataramanan