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@@ -31,9 +31,11 @@
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#include <linux/iio/triggered_buffer.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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+#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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+#include <linux/of_device.h>
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#include "stm32-adc-core.h"
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@@ -76,6 +78,78 @@
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#define STM32F4_DMA BIT(8)
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#define STM32F4_ADON BIT(0)
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+/* STM32H7 - Registers for each ADC instance */
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+#define STM32H7_ADC_ISR 0x00
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+#define STM32H7_ADC_IER 0x04
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+#define STM32H7_ADC_CR 0x08
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+#define STM32H7_ADC_CFGR 0x0C
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+#define STM32H7_ADC_PCSEL 0x1C
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+#define STM32H7_ADC_SQR1 0x30
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+#define STM32H7_ADC_SQR2 0x34
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+#define STM32H7_ADC_SQR3 0x38
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+#define STM32H7_ADC_SQR4 0x3C
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+#define STM32H7_ADC_DR 0x40
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+#define STM32H7_ADC_CALFACT 0xC4
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+#define STM32H7_ADC_CALFACT2 0xC8
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+
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+/* STM32H7_ADC_ISR - bit fields */
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+#define STM32H7_EOC BIT(2)
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+#define STM32H7_ADRDY BIT(0)
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+
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+/* STM32H7_ADC_IER - bit fields */
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+#define STM32H7_EOCIE STM32H7_EOC
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+
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+/* STM32H7_ADC_CR - bit fields */
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+#define STM32H7_ADCAL BIT(31)
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+#define STM32H7_ADCALDIF BIT(30)
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+#define STM32H7_DEEPPWD BIT(29)
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+#define STM32H7_ADVREGEN BIT(28)
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+#define STM32H7_LINCALRDYW6 BIT(27)
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+#define STM32H7_LINCALRDYW5 BIT(26)
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+#define STM32H7_LINCALRDYW4 BIT(25)
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+#define STM32H7_LINCALRDYW3 BIT(24)
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+#define STM32H7_LINCALRDYW2 BIT(23)
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+#define STM32H7_LINCALRDYW1 BIT(22)
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+#define STM32H7_ADCALLIN BIT(16)
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+#define STM32H7_BOOST BIT(8)
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+#define STM32H7_ADSTP BIT(4)
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+#define STM32H7_ADSTART BIT(2)
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+#define STM32H7_ADDIS BIT(1)
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+#define STM32H7_ADEN BIT(0)
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+
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+/* STM32H7_ADC_CFGR bit fields */
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+#define STM32H7_EXTEN_SHIFT 10
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+#define STM32H7_EXTEN_MASK GENMASK(11, 10)
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+#define STM32H7_EXTSEL_SHIFT 5
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+#define STM32H7_EXTSEL_MASK GENMASK(9, 5)
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+#define STM32H7_RES_SHIFT 2
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+#define STM32H7_RES_MASK GENMASK(4, 2)
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+#define STM32H7_DMNGT_SHIFT 0
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+#define STM32H7_DMNGT_MASK GENMASK(1, 0)
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+
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+enum stm32h7_adc_dmngt {
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+ STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
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+ STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
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+ STM32H7_DMNGT_DFSDM, /* DFSDM mode */
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+ STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
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+};
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+
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+/* STM32H7_ADC_CALFACT - bit fields */
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+#define STM32H7_CALFACT_D_SHIFT 16
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+#define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
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+#define STM32H7_CALFACT_S_SHIFT 0
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+#define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
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+
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+/* STM32H7_ADC_CALFACT2 - bit fields */
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+#define STM32H7_LINCALFACT_SHIFT 0
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+#define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
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+
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+/* Number of linear calibration shadow registers / LINCALRDYW control bits */
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+#define STM32H7_LINCALFACT_NUM 6
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+
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+/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
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+#define STM32H7_BOOST_CLKRATE 20000000UL
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+
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#define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
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#define STM32_ADC_TIMEOUT_US 100000
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#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
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@@ -120,6 +194,18 @@ struct stm32_adc_trig_info {
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enum stm32_adc_extsel extsel;
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};
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+/**
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+ * struct stm32_adc_calib - optional adc calibration data
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+ * @calfact_s: Calibration offset for single ended channels
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+ * @calfact_d: Calibration offset in differential
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+ * @lincalfact: Linearity calibration factor
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+ */
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+struct stm32_adc_calib {
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+ u32 calfact_s;
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+ u32 calfact_d;
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+ u32 lincalfact[STM32H7_LINCALFACT_NUM];
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+};
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+
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/**
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* stm32_adc_regs - stm32 ADC misc registers & bitfield desc
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* @reg: register offset
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@@ -132,10 +218,57 @@ struct stm32_adc_regs {
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int shift;
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};
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+/**
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+ * stm32_adc_regspec - stm32 registers definition, compatible dependent data
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+ * @dr: data register offset
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+ * @ier_eoc: interrupt enable register & eocie bitfield
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+ * @isr_eoc: interrupt status register & eoc bitfield
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+ * @sqr: reference to sequence registers array
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+ * @exten: trigger control register & bitfield
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+ * @extsel: trigger selection register & bitfield
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+ * @res: resolution selection register & bitfield
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+ */
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+struct stm32_adc_regspec {
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+ const u32 dr;
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+ const struct stm32_adc_regs ier_eoc;
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+ const struct stm32_adc_regs isr_eoc;
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+ const struct stm32_adc_regs *sqr;
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+ const struct stm32_adc_regs exten;
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+ const struct stm32_adc_regs extsel;
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+ const struct stm32_adc_regs res;
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+};
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+
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+struct stm32_adc;
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+
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+/**
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+ * stm32_adc_cfg - stm32 compatible configuration data
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+ * @regs: registers descriptions
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+ * @adc_info: per instance input channels definitions
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+ * @trigs: external trigger sources
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+ * @clk_required: clock is required
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+ * @selfcalib: optional routine for self-calibration
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+ * @prepare: optional prepare routine (power-up, enable)
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+ * @start_conv: routine to start conversions
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+ * @stop_conv: routine to stop conversions
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+ * @unprepare: optional unprepare routine (disable, power-down)
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+ */
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+struct stm32_adc_cfg {
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+ const struct stm32_adc_regspec *regs;
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+ const struct stm32_adc_info *adc_info;
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+ struct stm32_adc_trig_info *trigs;
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+ bool clk_required;
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+ int (*selfcalib)(struct stm32_adc *);
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+ int (*prepare)(struct stm32_adc *);
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+ void (*start_conv)(struct stm32_adc *, bool dma);
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+ void (*stop_conv)(struct stm32_adc *);
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+ void (*unprepare)(struct stm32_adc *);
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+};
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+
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/**
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* struct stm32_adc - private data of each ADC IIO instance
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* @common: reference to ADC block common data
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* @offset: ADC instance register offset in ADC block
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+ * @cfg: compatible configuration data
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* @completion: end of single conversion completion
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* @buffer: data buffer
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* @clk: clock for this adc instance
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@@ -149,10 +282,13 @@ struct stm32_adc_regs {
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* @rx_buf: dma rx buffer cpu address
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* @rx_dma_buf: dma rx buffer bus address
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* @rx_buf_sz: dma rx buffer size
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+ * @pcsel bitmask to preselect channels on some devices
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+ * @cal: optional calibration data on some devices
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*/
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struct stm32_adc {
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struct stm32_adc_common *common;
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u32 offset;
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+ const struct stm32_adc_cfg *cfg;
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struct completion completion;
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u16 buffer[STM32_ADC_MAX_SQ];
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struct clk *clk;
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@@ -166,6 +302,8 @@ struct stm32_adc {
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u8 *rx_buf;
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dma_addr_t rx_dma_buf;
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unsigned int rx_buf_sz;
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+ u32 pcsel;
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+ struct stm32_adc_calib cal;
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};
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/**
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@@ -180,8 +318,26 @@ struct stm32_adc_chan_spec {
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const char *name;
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};
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-/* Input definitions common for all STM32F4 instances */
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-static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
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+/**
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+ * struct stm32_adc_info - stm32 ADC, per instance config data
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+ * @channels: Reference to stm32 channels spec
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+ * @max_channels: Number of channels
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+ * @resolutions: available resolutions
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+ * @num_res: number of available resolutions
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+ */
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+struct stm32_adc_info {
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+ const struct stm32_adc_chan_spec *channels;
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+ int max_channels;
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+ const unsigned int *resolutions;
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+ const unsigned int num_res;
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+};
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+
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+/*
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+ * Input definitions common for all instances:
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+ * stm32f4 can have up to 16 channels
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+ * stm32h7 can have up to 20 channels
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+ */
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+static const struct stm32_adc_chan_spec stm32_adc_channels[] = {
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{ IIO_VOLTAGE, 0, "in0" },
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{ IIO_VOLTAGE, 1, "in1" },
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{ IIO_VOLTAGE, 2, "in2" },
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@@ -198,6 +354,10 @@ static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
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{ IIO_VOLTAGE, 13, "in13" },
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{ IIO_VOLTAGE, 14, "in14" },
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{ IIO_VOLTAGE, 15, "in15" },
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+ { IIO_VOLTAGE, 16, "in16" },
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+ { IIO_VOLTAGE, 17, "in17" },
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+ { IIO_VOLTAGE, 18, "in18" },
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+ { IIO_VOLTAGE, 19, "in19" },
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};
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static const unsigned int stm32f4_adc_resolutions[] = {
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@@ -205,6 +365,25 @@ static const unsigned int stm32f4_adc_resolutions[] = {
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12, 10, 8, 6,
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};
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+static const struct stm32_adc_info stm32f4_adc_info = {
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+ .channels = stm32_adc_channels,
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+ .max_channels = 16,
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+ .resolutions = stm32f4_adc_resolutions,
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+ .num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
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+};
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+
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+static const unsigned int stm32h7_adc_resolutions[] = {
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+ /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
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+ 16, 14, 12, 10, 8,
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+};
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+
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+static const struct stm32_adc_info stm32h7_adc_info = {
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+ .channels = stm32_adc_channels,
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+ .max_channels = 20,
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+ .resolutions = stm32h7_adc_resolutions,
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+ .num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
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+};
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+
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/**
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* stm32f4_sq - describe regular sequence registers
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* - L: sequence len (register & bit field)
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@@ -252,6 +431,69 @@ static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
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{}, /* sentinel */
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};
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+static const struct stm32_adc_regspec stm32f4_adc_regspec = {
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+ .dr = STM32F4_ADC_DR,
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+ .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
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+ .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
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+ .sqr = stm32f4_sq,
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+ .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
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+ .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
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+ STM32F4_EXTSEL_SHIFT },
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+ .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
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+};
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+
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+static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
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+ /* L: len bit field description to be kept as first element */
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+ { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
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+ /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
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+ { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
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+ { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
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+ { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
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+ { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
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+ { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
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+ { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
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+ { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
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+ { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
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+ { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
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+ { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
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+ { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
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+ { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
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+ { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
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+ { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
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+ { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
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+ { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
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+};
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+
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+/* STM32H7 external trigger sources for all instances */
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+static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
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+ { TIM1_CH1, STM32_EXT0 },
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+ { TIM1_CH2, STM32_EXT1 },
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+ { TIM1_CH3, STM32_EXT2 },
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+ { TIM2_CH2, STM32_EXT3 },
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+ { TIM3_TRGO, STM32_EXT4 },
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+ { TIM4_CH4, STM32_EXT5 },
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+ { TIM8_TRGO, STM32_EXT7 },
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+ { TIM8_TRGO2, STM32_EXT8 },
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+ { TIM1_TRGO, STM32_EXT9 },
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+ { TIM1_TRGO2, STM32_EXT10 },
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+ { TIM2_TRGO, STM32_EXT11 },
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+ { TIM4_TRGO, STM32_EXT12 },
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+ { TIM6_TRGO, STM32_EXT13 },
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+ { TIM3_CH4, STM32_EXT15 },
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+ {},
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+};
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+
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+static const struct stm32_adc_regspec stm32h7_adc_regspec = {
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+ .dr = STM32H7_ADC_DR,
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+ .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
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+ .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
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+ .sqr = stm32h7_sq,
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+ .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
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+ .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
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+ STM32H7_EXTSEL_SHIFT },
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+ .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
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+};
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+
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/**
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* STM32 ADC registers access routines
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* @adc: stm32 adc instance
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@@ -265,6 +507,12 @@ static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
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return readl_relaxed(adc->common->base + adc->offset + reg);
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}
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+#define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
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+
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+#define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
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+ readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
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+ cond, sleep_us, timeout_us)
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+
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static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
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{
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return readw_relaxed(adc->common->base + adc->offset + reg);
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@@ -299,7 +547,8 @@ static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
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*/
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static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
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{
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|
- stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
|
|
|
+ stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
|
|
|
+ adc->cfg->regs->ier_eoc.mask);
|
|
|
};
|
|
|
|
|
|
/**
|
|
|
@@ -308,19 +557,22 @@ static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
|
|
|
*/
|
|
|
static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
|
|
|
{
|
|
|
- stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
|
|
|
+ stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
|
|
|
+ adc->cfg->regs->ier_eoc.mask);
|
|
|
}
|
|
|
|
|
|
static void stm32_adc_set_res(struct stm32_adc *adc)
|
|
|
{
|
|
|
- u32 val = stm32_adc_readl(adc, STM32F4_ADC_CR1);
|
|
|
+ const struct stm32_adc_regs *res = &adc->cfg->regs->res;
|
|
|
+ u32 val;
|
|
|
|
|
|
- val = (val & ~STM32F4_RES_MASK) | (adc->res << STM32F4_RES_SHIFT);
|
|
|
- stm32_adc_writel(adc, STM32F4_ADC_CR1, val);
|
|
|
+ val = stm32_adc_readl(adc, res->reg);
|
|
|
+ val = (val & ~res->mask) | (adc->res << res->shift);
|
|
|
+ stm32_adc_writel(adc, res->reg, val);
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
- * stm32_adc_start_conv() - Start conversions for regular channels.
|
|
|
+ * stm32f4_adc_start_conv() - Start conversions for regular channels.
|
|
|
* @adc: stm32 adc instance
|
|
|
* @dma: use dma to transfer conversion result
|
|
|
*
|
|
|
@@ -329,7 +581,7 @@ static void stm32_adc_set_res(struct stm32_adc *adc)
|
|
|
* conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
|
|
|
* DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
|
|
|
*/
|
|
|
-static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma)
|
|
|
+static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma)
|
|
|
{
|
|
|
stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
|
|
|
|
|
|
@@ -347,7 +599,7 @@ static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma)
|
|
|
stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
|
|
|
}
|
|
|
|
|
|
-static void stm32_adc_stop_conv(struct stm32_adc *adc)
|
|
|
+static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
|
|
|
{
|
|
|
stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
|
|
|
stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
|
|
|
@@ -357,6 +609,324 @@ static void stm32_adc_stop_conv(struct stm32_adc *adc)
|
|
|
STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
|
|
|
}
|
|
|
|
|
|
+static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma)
|
|
|
+{
|
|
|
+ enum stm32h7_adc_dmngt dmngt;
|
|
|
+ unsigned long flags;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ if (dma)
|
|
|
+ dmngt = STM32H7_DMNGT_DMA_CIRC;
|
|
|
+ else
|
|
|
+ dmngt = STM32H7_DMNGT_DR_ONLY;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&adc->lock, flags);
|
|
|
+ val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
|
|
|
+ val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
|
|
|
+ stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
|
|
|
+ spin_unlock_irqrestore(&adc->lock, flags);
|
|
|
+
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
|
|
+ int ret;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
|
|
|
+
|
|
|
+ ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
|
|
+ !(val & (STM32H7_ADSTART)),
|
|
|
+ 100, STM32_ADC_TIMEOUT_US);
|
|
|
+ if (ret)
|
|
|
+ dev_warn(&indio_dev->dev, "stop failed\n");
|
|
|
+
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ /* Exit deep power down, then enable ADC voltage regulator */
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
|
|
|
+
|
|
|
+ if (adc->common->rate > STM32H7_BOOST_CLKRATE)
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
|
|
|
+
|
|
|
+ /* Wait for startup time */
|
|
|
+ usleep_range(10, 20);
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
|
|
|
+
|
|
|
+ /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
|
|
|
+}
|
|
|
+
|
|
|
+static int stm32h7_adc_enable(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
|
|
+ int ret;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ /* Clear ADRDY by writing one, then enable ADC */
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
|
|
|
+
|
|
|
+ /* Poll for ADRDY to be set (after adc startup time) */
|
|
|
+ ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
|
|
|
+ val & STM32H7_ADRDY,
|
|
|
+ 100, STM32_ADC_TIMEOUT_US);
|
|
|
+ if (ret) {
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
|
|
|
+ dev_err(&indio_dev->dev, "Failed to enable ADC\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32h7_adc_disable(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
|
|
+ int ret;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ /* Disable ADC and wait until it's effectively disabled */
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
|
|
|
+ ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
|
|
+ !(val & STM32H7_ADEN), 100,
|
|
|
+ STM32_ADC_TIMEOUT_US);
|
|
|
+ if (ret)
|
|
|
+ dev_warn(&indio_dev->dev, "Failed to disable\n");
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
|
|
|
+ * @adc: stm32 adc instance
|
|
|
+ */
|
|
|
+static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
|
|
+ int i, ret;
|
|
|
+ u32 lincalrdyw_mask, val;
|
|
|
+
|
|
|
+ /* Enable adc so LINCALRDYW1..6 bits are writable */
|
|
|
+ ret = stm32h7_adc_enable(adc);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ /* Read linearity calibration */
|
|
|
+ lincalrdyw_mask = STM32H7_LINCALRDYW6;
|
|
|
+ for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
|
|
|
+ /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
|
|
|
+
|
|
|
+ /* Poll: wait calib data to be ready in CALFACT2 register */
|
|
|
+ ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
|
|
+ !(val & lincalrdyw_mask),
|
|
|
+ 100, STM32_ADC_TIMEOUT_US);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&indio_dev->dev, "Failed to read calfact\n");
|
|
|
+ goto disable;
|
|
|
+ }
|
|
|
+
|
|
|
+ val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
|
|
|
+ adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
|
|
|
+ adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
|
|
|
+
|
|
|
+ lincalrdyw_mask >>= 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Read offset calibration */
|
|
|
+ val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
|
|
|
+ adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
|
|
|
+ adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
|
|
|
+ adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
|
|
|
+ adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
|
|
|
+
|
|
|
+disable:
|
|
|
+ stm32h7_adc_disable(adc);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
|
|
|
+ * @adc: stm32 adc instance
|
|
|
+ * Note: ADC must be enabled, with no on-going conversions.
|
|
|
+ */
|
|
|
+static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
|
|
+ int i, ret;
|
|
|
+ u32 lincalrdyw_mask, val;
|
|
|
+
|
|
|
+ val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
|
|
|
+ (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
|
|
|
+ stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
|
|
|
+
|
|
|
+ lincalrdyw_mask = STM32H7_LINCALRDYW6;
|
|
|
+ for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
|
|
|
+ /*
|
|
|
+ * Write saved calibration data to shadow registers:
|
|
|
+ * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
|
|
|
+ * data write. Then poll to wait for complete transfer.
|
|
|
+ */
|
|
|
+ val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
|
|
|
+ stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
|
|
|
+ ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
|
|
+ val & lincalrdyw_mask,
|
|
|
+ 100, STM32_ADC_TIMEOUT_US);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&indio_dev->dev, "Failed to write calfact\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Read back calibration data, has two effects:
|
|
|
+ * - It ensures bits LINCALRDYW[6..1] are kept cleared
|
|
|
+ * for next time calibration needs to be restored.
|
|
|
+ * - BTW, bit clear triggers a read, then check data has been
|
|
|
+ * correctly written.
|
|
|
+ */
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
|
|
|
+ ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
|
|
+ !(val & lincalrdyw_mask),
|
|
|
+ 100, STM32_ADC_TIMEOUT_US);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&indio_dev->dev, "Failed to read calfact\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
|
|
|
+ if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
|
|
|
+ dev_err(&indio_dev->dev, "calfact not consistent\n");
|
|
|
+ return -EIO;
|
|
|
+ }
|
|
|
+
|
|
|
+ lincalrdyw_mask >>= 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * Fixed timeout value for ADC calibration.
|
|
|
+ * worst cases:
|
|
|
+ * - low clock frequency
|
|
|
+ * - maximum prescalers
|
|
|
+ * Calibration requires:
|
|
|
+ * - 131,072 ADC clock cycle for the linear calibration
|
|
|
+ * - 20 ADC clock cycle for the offset calibration
|
|
|
+ *
|
|
|
+ * Set to 100ms for now
|
|
|
+ */
|
|
|
+#define STM32H7_ADC_CALIB_TIMEOUT_US 100000
|
|
|
+
|
|
|
+/**
|
|
|
+ * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down)
|
|
|
+ * @adc: stm32 adc instance
|
|
|
+ * Exit from power down, calibrate ADC, then return to power down.
|
|
|
+ */
|
|
|
+static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
|
|
+ int ret;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ stm32h7_adc_exit_pwr_down(adc);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Select calibration mode:
|
|
|
+ * - Offset calibration for single ended inputs
|
|
|
+ * - No linearity calibration (do it later, before reading it)
|
|
|
+ */
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
|
|
|
+
|
|
|
+ /* Start calibration, then wait for completion */
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
|
|
|
+ ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
|
|
+ !(val & STM32H7_ADCAL), 100,
|
|
|
+ STM32H7_ADC_CALIB_TIMEOUT_US);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&indio_dev->dev, "calibration failed\n");
|
|
|
+ goto pwr_dwn;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Select calibration mode, then start calibration:
|
|
|
+ * - Offset calibration for differential input
|
|
|
+ * - Linearity calibration (needs to be done only once for single/diff)
|
|
|
+ * will run simultaneously with offset calibration.
|
|
|
+ */
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR,
|
|
|
+ STM32H7_ADCALDIF | STM32H7_ADCALLIN);
|
|
|
+ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
|
|
|
+ ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
|
|
|
+ !(val & STM32H7_ADCAL), 100,
|
|
|
+ STM32H7_ADC_CALIB_TIMEOUT_US);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&indio_dev->dev, "calibration failed\n");
|
|
|
+ goto pwr_dwn;
|
|
|
+ }
|
|
|
+
|
|
|
+ stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
|
|
|
+ STM32H7_ADCALDIF | STM32H7_ADCALLIN);
|
|
|
+
|
|
|
+ /* Read calibration result for future reference */
|
|
|
+ ret = stm32h7_adc_read_selfcalib(adc);
|
|
|
+
|
|
|
+pwr_dwn:
|
|
|
+ stm32h7_adc_enter_pwr_down(adc);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
|
|
|
+ * @adc: stm32 adc instance
|
|
|
+ * Leave power down mode.
|
|
|
+ * Enable ADC.
|
|
|
+ * Restore calibration data.
|
|
|
+ * Pre-select channels that may be used in PCSEL (required by input MUX / IO).
|
|
|
+ */
|
|
|
+static int stm32h7_adc_prepare(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ stm32h7_adc_exit_pwr_down(adc);
|
|
|
+
|
|
|
+ ret = stm32h7_adc_enable(adc);
|
|
|
+ if (ret)
|
|
|
+ goto pwr_dwn;
|
|
|
+
|
|
|
+ ret = stm32h7_adc_restore_selfcalib(adc);
|
|
|
+ if (ret)
|
|
|
+ goto disable;
|
|
|
+
|
|
|
+ stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+disable:
|
|
|
+ stm32h7_adc_disable(adc);
|
|
|
+pwr_dwn:
|
|
|
+ stm32h7_adc_enter_pwr_down(adc);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32h7_adc_unprepare(struct stm32_adc *adc)
|
|
|
+{
|
|
|
+ stm32h7_adc_disable(adc);
|
|
|
+ stm32h7_adc_enter_pwr_down(adc);
|
|
|
+}
|
|
|
+
|
|
|
/**
|
|
|
* stm32_adc_conf_scan_seq() - Build regular channels scan sequence
|
|
|
* @indio_dev: IIO device
|
|
|
@@ -371,6 +941,7 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
|
|
|
const unsigned long *scan_mask)
|
|
|
{
|
|
|
struct stm32_adc *adc = iio_priv(indio_dev);
|
|
|
+ const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
|
|
|
const struct iio_chan_spec *chan;
|
|
|
u32 val, bit;
|
|
|
int i = 0;
|
|
|
@@ -388,20 +959,20 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
|
|
|
dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
|
|
|
__func__, chan->channel, i);
|
|
|
|
|
|
- val = stm32_adc_readl(adc, stm32f4_sq[i].reg);
|
|
|
- val &= ~stm32f4_sq[i].mask;
|
|
|
- val |= chan->channel << stm32f4_sq[i].shift;
|
|
|
- stm32_adc_writel(adc, stm32f4_sq[i].reg, val);
|
|
|
+ val = stm32_adc_readl(adc, sqr[i].reg);
|
|
|
+ val &= ~sqr[i].mask;
|
|
|
+ val |= chan->channel << sqr[i].shift;
|
|
|
+ stm32_adc_writel(adc, sqr[i].reg, val);
|
|
|
}
|
|
|
|
|
|
if (!i)
|
|
|
return -EINVAL;
|
|
|
|
|
|
/* Sequence len */
|
|
|
- val = stm32_adc_readl(adc, stm32f4_sq[0].reg);
|
|
|
- val &= ~stm32f4_sq[0].mask;
|
|
|
- val |= ((i - 1) << stm32f4_sq[0].shift);
|
|
|
- stm32_adc_writel(adc, stm32f4_sq[0].reg, val);
|
|
|
+ val = stm32_adc_readl(adc, sqr[0].reg);
|
|
|
+ val &= ~sqr[0].mask;
|
|
|
+ val |= ((i - 1) << sqr[0].shift);
|
|
|
+ stm32_adc_writel(adc, sqr[0].reg, val);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
@@ -412,19 +983,21 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
|
|
|
*
|
|
|
* Returns trigger extsel value, if trig matches, -EINVAL otherwise.
|
|
|
*/
|
|
|
-static int stm32_adc_get_trig_extsel(struct iio_trigger *trig)
|
|
|
+static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
|
|
|
+ struct iio_trigger *trig)
|
|
|
{
|
|
|
+ struct stm32_adc *adc = iio_priv(indio_dev);
|
|
|
int i;
|
|
|
|
|
|
/* lookup triggers registered by stm32 timer trigger driver */
|
|
|
- for (i = 0; stm32f4_adc_trigs[i].name; i++) {
|
|
|
+ for (i = 0; adc->cfg->trigs[i].name; i++) {
|
|
|
/**
|
|
|
* Checking both stm32 timer trigger type and trig name
|
|
|
* should be safe against arbitrary trigger names.
|
|
|
*/
|
|
|
if (is_stm32_timer_trigger(trig) &&
|
|
|
- !strcmp(stm32f4_adc_trigs[i].name, trig->name)) {
|
|
|
- return stm32f4_adc_trigs[i].extsel;
|
|
|
+ !strcmp(adc->cfg->trigs[i].name, trig->name)) {
|
|
|
+ return adc->cfg->trigs[i].extsel;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
@@ -449,7 +1022,7 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev,
|
|
|
int ret;
|
|
|
|
|
|
if (trig) {
|
|
|
- ret = stm32_adc_get_trig_extsel(trig);
|
|
|
+ ret = stm32_adc_get_trig_extsel(indio_dev, trig);
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
|
|
|
@@ -459,11 +1032,11 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev,
|
|
|
}
|
|
|
|
|
|
spin_lock_irqsave(&adc->lock, flags);
|
|
|
- val = stm32_adc_readl(adc, STM32F4_ADC_CR2);
|
|
|
- val &= ~(STM32F4_EXTEN_MASK | STM32F4_EXTSEL_MASK);
|
|
|
- val |= exten << STM32F4_EXTEN_SHIFT;
|
|
|
- val |= extsel << STM32F4_EXTSEL_SHIFT;
|
|
|
- stm32_adc_writel(adc, STM32F4_ADC_CR2, val);
|
|
|
+ val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
|
|
|
+ val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
|
|
|
+ val |= exten << adc->cfg->regs->exten.shift;
|
|
|
+ val |= extsel << adc->cfg->regs->extsel.shift;
|
|
|
+ stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
|
|
|
spin_unlock_irqrestore(&adc->lock, flags);
|
|
|
|
|
|
return 0;
|
|
|
@@ -515,6 +1088,7 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
|
|
|
int *res)
|
|
|
{
|
|
|
struct stm32_adc *adc = iio_priv(indio_dev);
|
|
|
+ const struct stm32_adc_regspec *regs = adc->cfg->regs;
|
|
|
long timeout;
|
|
|
u32 val;
|
|
|
int ret;
|
|
|
@@ -523,21 +1097,27 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
|
|
|
|
|
|
adc->bufi = 0;
|
|
|
|
|
|
+ if (adc->cfg->prepare) {
|
|
|
+ ret = adc->cfg->prepare(adc);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
/* Program chan number in regular sequence (SQ1) */
|
|
|
- val = stm32_adc_readl(adc, stm32f4_sq[1].reg);
|
|
|
- val &= ~stm32f4_sq[1].mask;
|
|
|
- val |= chan->channel << stm32f4_sq[1].shift;
|
|
|
- stm32_adc_writel(adc, stm32f4_sq[1].reg, val);
|
|
|
+ val = stm32_adc_readl(adc, regs->sqr[1].reg);
|
|
|
+ val &= ~regs->sqr[1].mask;
|
|
|
+ val |= chan->channel << regs->sqr[1].shift;
|
|
|
+ stm32_adc_writel(adc, regs->sqr[1].reg, val);
|
|
|
|
|
|
/* Set regular sequence len (0 for 1 conversion) */
|
|
|
- stm32_adc_clr_bits(adc, stm32f4_sq[0].reg, stm32f4_sq[0].mask);
|
|
|
+ stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
|
|
|
|
|
|
/* Trigger detection disabled (conversion can be launched in SW) */
|
|
|
- stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
|
|
|
+ stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
|
|
|
|
|
|
stm32_adc_conv_irq_enable(adc);
|
|
|
|
|
|
- stm32_adc_start_conv(adc, false);
|
|
|
+ adc->cfg->start_conv(adc, false);
|
|
|
|
|
|
timeout = wait_for_completion_interruptible_timeout(
|
|
|
&adc->completion, STM32_ADC_TIMEOUT);
|
|
|
@@ -550,10 +1130,13 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
|
|
|
ret = IIO_VAL_INT;
|
|
|
}
|
|
|
|
|
|
- stm32_adc_stop_conv(adc);
|
|
|
+ adc->cfg->stop_conv(adc);
|
|
|
|
|
|
stm32_adc_conv_irq_disable(adc);
|
|
|
|
|
|
+ if (adc->cfg->unprepare)
|
|
|
+ adc->cfg->unprepare(adc);
|
|
|
+
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
@@ -590,11 +1173,12 @@ static irqreturn_t stm32_adc_isr(int irq, void *data)
|
|
|
{
|
|
|
struct stm32_adc *adc = data;
|
|
|
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
|
|
- u32 status = stm32_adc_readl(adc, STM32F4_ADC_SR);
|
|
|
+ const struct stm32_adc_regspec *regs = adc->cfg->regs;
|
|
|
+ u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
|
|
|
|
|
|
- if (status & STM32F4_EOC) {
|
|
|
+ if (status & regs->isr_eoc.mask) {
|
|
|
/* Reading DR also clears EOC status flag */
|
|
|
- adc->buffer[adc->bufi] = stm32_adc_readw(adc, STM32F4_ADC_DR);
|
|
|
+ adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
|
|
|
if (iio_buffer_enabled(indio_dev)) {
|
|
|
adc->bufi++;
|
|
|
if (adc->bufi >= adc->num_conv) {
|
|
|
@@ -621,7 +1205,7 @@ static irqreturn_t stm32_adc_isr(int irq, void *data)
|
|
|
static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
|
|
|
struct iio_trigger *trig)
|
|
|
{
|
|
|
- return stm32_adc_get_trig_extsel(trig) < 0 ? -EINVAL : 0;
|
|
|
+ return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
|
|
|
}
|
|
|
|
|
|
static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
|
|
|
@@ -777,10 +1361,16 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
|
|
|
struct stm32_adc *adc = iio_priv(indio_dev);
|
|
|
int ret;
|
|
|
|
|
|
+ if (adc->cfg->prepare) {
|
|
|
+ ret = adc->cfg->prepare(adc);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
|
|
|
if (ret) {
|
|
|
dev_err(&indio_dev->dev, "Can't set trigger\n");
|
|
|
- return ret;
|
|
|
+ goto err_unprepare;
|
|
|
}
|
|
|
|
|
|
ret = stm32_adc_dma_start(indio_dev);
|
|
|
@@ -799,7 +1389,7 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
|
|
|
if (!adc->dma_chan)
|
|
|
stm32_adc_conv_irq_enable(adc);
|
|
|
|
|
|
- stm32_adc_start_conv(adc, !!adc->dma_chan);
|
|
|
+ adc->cfg->start_conv(adc, !!adc->dma_chan);
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
@@ -808,6 +1398,9 @@ err_stop_dma:
|
|
|
dmaengine_terminate_all(adc->dma_chan);
|
|
|
err_clr_trig:
|
|
|
stm32_adc_set_trig(indio_dev, NULL);
|
|
|
+err_unprepare:
|
|
|
+ if (adc->cfg->unprepare)
|
|
|
+ adc->cfg->unprepare(adc);
|
|
|
|
|
|
return ret;
|
|
|
}
|
|
|
@@ -817,7 +1410,7 @@ static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
|
|
|
struct stm32_adc *adc = iio_priv(indio_dev);
|
|
|
int ret;
|
|
|
|
|
|
- stm32_adc_stop_conv(adc);
|
|
|
+ adc->cfg->stop_conv(adc);
|
|
|
if (!adc->dma_chan)
|
|
|
stm32_adc_conv_irq_disable(adc);
|
|
|
|
|
|
@@ -831,6 +1424,9 @@ static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
|
|
|
if (stm32_adc_set_trig(indio_dev, NULL))
|
|
|
dev_err(&indio_dev->dev, "Can't clear trigger\n");
|
|
|
|
|
|
+ if (adc->cfg->unprepare)
|
|
|
+ adc->cfg->unprepare(adc);
|
|
|
+
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
@@ -895,12 +1491,12 @@ static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
|
|
|
u32 res;
|
|
|
|
|
|
if (of_property_read_u32(node, "assigned-resolution-bits", &res))
|
|
|
- res = stm32f4_adc_resolutions[0];
|
|
|
+ res = adc->cfg->adc_info->resolutions[0];
|
|
|
|
|
|
- for (i = 0; i < ARRAY_SIZE(stm32f4_adc_resolutions); i++)
|
|
|
- if (res == stm32f4_adc_resolutions[i])
|
|
|
+ for (i = 0; i < adc->cfg->adc_info->num_res; i++)
|
|
|
+ if (res == adc->cfg->adc_info->resolutions[i])
|
|
|
break;
|
|
|
- if (i >= ARRAY_SIZE(stm32f4_adc_resolutions)) {
|
|
|
+ if (i >= adc->cfg->adc_info->num_res) {
|
|
|
dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
@@ -926,14 +1522,19 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
|
|
|
chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
|
|
|
chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
|
|
|
chan->scan_type.sign = 'u';
|
|
|
- chan->scan_type.realbits = stm32f4_adc_resolutions[adc->res];
|
|
|
+ chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
|
|
|
chan->scan_type.storagebits = 16;
|
|
|
chan->ext_info = stm32_adc_ext_info;
|
|
|
+
|
|
|
+ /* pre-build selected channels mask */
|
|
|
+ adc->pcsel |= BIT(chan->channel);
|
|
|
}
|
|
|
|
|
|
static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
|
|
|
{
|
|
|
struct device_node *node = indio_dev->dev.of_node;
|
|
|
+ struct stm32_adc *adc = iio_priv(indio_dev);
|
|
|
+ const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
|
|
|
struct property *prop;
|
|
|
const __be32 *cur;
|
|
|
struct iio_chan_spec *channels;
|
|
|
@@ -942,7 +1543,7 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
|
|
|
|
|
|
num_channels = of_property_count_u32_elems(node, "st,adc-channels");
|
|
|
if (num_channels < 0 ||
|
|
|
- num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) {
|
|
|
+ num_channels >= adc_info->max_channels) {
|
|
|
dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
|
|
|
return num_channels < 0 ? num_channels : -EINVAL;
|
|
|
}
|
|
|
@@ -953,12 +1554,12 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
|
|
|
return -ENOMEM;
|
|
|
|
|
|
of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
|
|
|
- if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) {
|
|
|
+ if (val >= adc_info->max_channels) {
|
|
|
dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
|
|
|
- &stm32f4_adc123_channels[val],
|
|
|
+ &adc_info->channels[val],
|
|
|
scan_index);
|
|
|
scan_index++;
|
|
|
}
|
|
|
@@ -990,7 +1591,7 @@ static int stm32_adc_dma_request(struct iio_dev *indio_dev)
|
|
|
/* Configure DMA channel to read data register */
|
|
|
memset(&config, 0, sizeof(config));
|
|
|
config.src_addr = (dma_addr_t)adc->common->phys_base;
|
|
|
- config.src_addr += adc->offset + STM32F4_ADC_DR;
|
|
|
+ config.src_addr += adc->offset + adc->cfg->regs->dr;
|
|
|
config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
|
|
|
|
ret = dmaengine_slave_config(adc->dma_chan, &config);
|
|
|
@@ -1011,6 +1612,7 @@ err_release:
|
|
|
static int stm32_adc_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
struct iio_dev *indio_dev;
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
struct stm32_adc *adc;
|
|
|
int ret;
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@@ -1025,6 +1627,8 @@ static int stm32_adc_probe(struct platform_device *pdev)
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adc->common = dev_get_drvdata(pdev->dev.parent);
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spin_lock_init(&adc->lock);
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init_completion(&adc->completion);
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+ adc->cfg = (const struct stm32_adc_cfg *)
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+ of_match_device(dev->driver->of_match_table, dev)->data;
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indio_dev->name = dev_name(&pdev->dev);
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indio_dev->dev.parent = &pdev->dev;
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@@ -1055,14 +1659,21 @@ static int stm32_adc_probe(struct platform_device *pdev)
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adc->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(adc->clk)) {
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- dev_err(&pdev->dev, "Can't get clock\n");
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- return PTR_ERR(adc->clk);
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+ ret = PTR_ERR(adc->clk);
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+ if (ret == -ENOENT && !adc->cfg->clk_required) {
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+ adc->clk = NULL;
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+ } else {
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+ dev_err(&pdev->dev, "Can't get clock\n");
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+ return ret;
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+ }
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}
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- ret = clk_prepare_enable(adc->clk);
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- if (ret < 0) {
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- dev_err(&pdev->dev, "clk enable failed\n");
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- return ret;
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+ if (adc->clk) {
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+ ret = clk_prepare_enable(adc->clk);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "clk enable failed\n");
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+ return ret;
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+ }
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}
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ret = stm32_adc_of_get_resolution(indio_dev);
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@@ -1070,6 +1681,12 @@ static int stm32_adc_probe(struct platform_device *pdev)
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goto err_clk_disable;
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stm32_adc_set_res(adc);
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+ if (adc->cfg->selfcalib) {
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+ ret = adc->cfg->selfcalib(adc);
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+ if (ret)
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+ goto err_clk_disable;
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+ }
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+
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ret = stm32_adc_chan_of_init(indio_dev);
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if (ret < 0)
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goto err_clk_disable;
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@@ -1106,7 +1723,8 @@ err_dma_disable:
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dma_release_channel(adc->dma_chan);
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}
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err_clk_disable:
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- clk_disable_unprepare(adc->clk);
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+ if (adc->clk)
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+ clk_disable_unprepare(adc->clk);
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return ret;
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}
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@@ -1124,13 +1742,35 @@ static int stm32_adc_remove(struct platform_device *pdev)
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adc->rx_buf, adc->rx_dma_buf);
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dma_release_channel(adc->dma_chan);
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}
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- clk_disable_unprepare(adc->clk);
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+ if (adc->clk)
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+ clk_disable_unprepare(adc->clk);
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return 0;
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}
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+static const struct stm32_adc_cfg stm32f4_adc_cfg = {
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+ .regs = &stm32f4_adc_regspec,
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+ .adc_info = &stm32f4_adc_info,
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+ .trigs = stm32f4_adc_trigs,
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+ .clk_required = true,
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+ .start_conv = stm32f4_adc_start_conv,
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+ .stop_conv = stm32f4_adc_stop_conv,
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+};
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+
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+static const struct stm32_adc_cfg stm32h7_adc_cfg = {
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+ .regs = &stm32h7_adc_regspec,
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+ .adc_info = &stm32h7_adc_info,
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+ .trigs = stm32h7_adc_trigs,
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+ .selfcalib = stm32h7_adc_selfcalib,
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+ .start_conv = stm32h7_adc_start_conv,
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+ .stop_conv = stm32h7_adc_stop_conv,
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+ .prepare = stm32h7_adc_prepare,
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+ .unprepare = stm32h7_adc_unprepare,
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+};
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+
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static const struct of_device_id stm32_adc_of_match[] = {
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- { .compatible = "st,stm32f4-adc" },
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+ { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
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+ { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
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{},
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};
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MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
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Greg Kroah-Hartman