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@@ -203,9 +203,9 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
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#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
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#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
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-static void amdgpu_atombios_dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
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- int lane_count,
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- u8 train_set[4])
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+static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
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+ int lane_count,
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+ u8 train_set[4])
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{
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u8 v = 0;
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u8 p = 0;
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@@ -265,8 +265,8 @@ static int amdgpu_atombios_dp_get_max_dp_pix_clock(int link_rate,
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* if the max lane# < low rate lane# then use max lane# instead.
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*/
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static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector,
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- u8 dpcd[DP_DPCD_SIZE],
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- int pix_clock)
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+ const u8 dpcd[DP_DPCD_SIZE],
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+ int pix_clock)
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{
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int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
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int max_link_rate = drm_dp_max_link_rate(dpcd);
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@@ -284,8 +284,8 @@ static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector
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}
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static int amdgpu_atombios_dp_get_dp_link_clock(struct drm_connector *connector,
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- u8 dpcd[DP_DPCD_SIZE],
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- int pix_clock)
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+ const u8 dpcd[DP_DPCD_SIZE],
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+ int pix_clock)
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{
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int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
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int lane_num, max_pix_clock;
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