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@@ -598,7 +598,6 @@ static void handle_once_dma_done(struct tegra_dma_channel *tdc,
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return;
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tdc_start_head_req(tdc);
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- return;
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}
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static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
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@@ -625,7 +624,6 @@ static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
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if (!st)
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dma_desc->dma_status = DMA_ERROR;
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}
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- return;
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}
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static void tegra_dma_tasklet(unsigned long data)
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@@ -717,7 +715,6 @@ static void tegra_dma_issue_pending(struct dma_chan *dc)
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}
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end:
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spin_unlock_irqrestore(&tdc->lock, flags);
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- return;
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}
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static int tegra_dma_terminate_all(struct dma_chan *dc)
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@@ -929,7 +926,6 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
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struct tegra_dma_sg_req *sg_req = NULL;
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u32 burst_size;
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enum dma_slave_buswidth slave_bw;
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- int ret;
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if (!tdc->config_init) {
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dev_err(tdc2dev(tdc), "dma channel is not configured\n");
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@@ -940,9 +936,8 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
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return NULL;
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}
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- ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
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- &burst_size, &slave_bw);
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- if (ret < 0)
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+ if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
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+ &burst_size, &slave_bw) < 0)
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return NULL;
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INIT_LIST_HEAD(&req_list);
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@@ -1045,7 +1040,6 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
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dma_addr_t mem = buf_addr;
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u32 burst_size;
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enum dma_slave_buswidth slave_bw;
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- int ret;
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if (!buf_len || !period_len) {
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dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
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@@ -1084,12 +1078,10 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
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return NULL;
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}
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- ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
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- &burst_size, &slave_bw);
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- if (ret < 0)
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+ if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
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+ &burst_size, &slave_bw) < 0)
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return NULL;
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-
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ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
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ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
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TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
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