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@@ -4,7 +4,7 @@
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DSCR register in powerpc allows user to have some control of prefetch of data
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stream in the processor. Please refer to the ISA documents or related manual
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for more detailed information regarding how to use this DSCR to attain this
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-control of the pefetches . This document here provides an overview of kernel
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+control of the prefetches . This document here provides an overview of kernel
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support for DSCR, related kernel objects, it's functionalities and exported
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user interface.
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@@ -44,7 +44,7 @@ user interface.
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value into every CPU's DSCR register right away and updates the current
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thread's DSCR value as well.
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- Changing the CPU specif DSCR default value in the sysfs does exactly
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+ Changing the CPU specific DSCR default value in the sysfs does exactly
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the same thing as above but unlike the global one above, it just changes
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stuff for that particular CPU instead for all the CPUs on the system.
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@@ -62,7 +62,7 @@ user interface.
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Accessing DSCR through user level SPR (0x03) from user space will first
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create a facility unavailable exception. Inside this exception handler
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- all mfspr isntruction based read attempts will get emulated and returned
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+ all mfspr instruction based read attempts will get emulated and returned
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where as the first mtspr instruction based write attempts will enable
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the DSCR facility for the next time around (both for read and write) by
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setting DSCR facility in the FSCR register.
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