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@@ -417,6 +417,40 @@ void dss_mgr_start_update(struct omap_overlay_manager *mgr)
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dispc_mgr_enable(mgr->id, true);
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}
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+static void dss_apply_irq_handler(void *data, u32 mask);
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+
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+static void dss_register_vsync_isr(void)
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+{
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+ u32 mask;
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+ int r;
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+
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+ mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
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+ DISPC_IRQ_EVSYNC_EVEN;
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+ if (dss_has_feature(FEAT_MGR_LCD2))
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+ mask |= DISPC_IRQ_VSYNC2;
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+
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+ r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
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+ WARN_ON(r);
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+
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+ dss_cache.irq_enabled = true;
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+}
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+
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+static void dss_unregister_vsync_isr(void)
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+{
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+ u32 mask;
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+ int r;
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+
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+ mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
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+ DISPC_IRQ_EVSYNC_EVEN;
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+ if (dss_has_feature(FEAT_MGR_LCD2))
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+ mask |= DISPC_IRQ_VSYNC2;
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+
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+ r = omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, mask);
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+ WARN_ON(r);
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+
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+ dss_cache.irq_enabled = false;
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+}
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+
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static void dss_apply_irq_handler(void *data, u32 mask)
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{
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struct manager_cache_data *mc;
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@@ -425,7 +459,6 @@ static void dss_apply_irq_handler(void *data, u32 mask)
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const int num_mgrs = dss_feat_get_num_mgrs();
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int i, r;
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bool mgr_busy[MAX_DSS_MANAGERS];
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- u32 irq_mask;
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for (i = 0; i < num_mgrs; i++)
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mgr_busy[i] = dispc_mgr_go_busy(i);
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@@ -459,13 +492,7 @@ static void dss_apply_irq_handler(void *data, u32 mask)
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goto end;
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}
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- irq_mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
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- DISPC_IRQ_EVSYNC_EVEN;
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- if (dss_has_feature(FEAT_MGR_LCD2))
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- irq_mask |= DISPC_IRQ_VSYNC2;
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-
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- omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, irq_mask);
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- dss_cache.irq_enabled = false;
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+ dss_unregister_vsync_isr();
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end:
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spin_unlock(&dss_cache.lock);
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@@ -605,22 +632,8 @@ int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
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r = 0;
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if (mgr->enabled && !mgr_manual_update(mgr)) {
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- if (!dss_cache.irq_enabled) {
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- u32 mask;
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-
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- mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
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- DISPC_IRQ_EVSYNC_EVEN;
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- if (dss_has_feature(FEAT_MGR_LCD2))
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- mask |= DISPC_IRQ_VSYNC2;
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-
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- r = omap_dispc_register_isr(dss_apply_irq_handler,
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- NULL, mask);
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-
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- if (r)
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- DSSERR("failed to register apply isr\n");
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-
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- dss_cache.irq_enabled = true;
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- }
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+ if (!dss_cache.irq_enabled)
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+ dss_register_vsync_isr();
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configure_dispc();
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}
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