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drm/amdgpu: fix Vega10 HW config for 2MB pages

Those values weren't correct. This should result in quite some speedup.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König 8 years ago
parent
a35ebc8c12
commit
dbcca4aab1
2 changed files with 4 additions and 4 deletions
Split View Show Diff Stats
  1. 2 2
      drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
  2. 2 2
      drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+ 2 - 2
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
View File 

@@ -144,8 +144,8 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 
 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
 
 
 	tmp = mmVM_L2_CNTL3_DEFAULT;
 
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 
 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
 
 
 	tmp = mmVM_L2_CNTL4_DEFAULT;

+ 2 - 2
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
View File 

@@ -158,8 +158,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 
 	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
 
 
 	tmp = mmVM_L2_CNTL3_DEFAULT;
 
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 
 	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
 
 
 	tmp = mmVM_L2_CNTL4_DEFAULT;