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@@ -395,7 +395,6 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
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/* Enable the pool VP */
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vp = xive_pool_vps + cpu;
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- pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
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for (;;) {
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rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
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if (rc != OPAL_BUSY)
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@@ -415,16 +414,9 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
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}
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vp_cam = be64_to_cpu(vp_cam_be);
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- pr_debug("VP CAM = %llx\n", vp_cam);
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-
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/* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
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- pr_debug("(Old HW value: %08x)\n",
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- in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
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out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
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- out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
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- TM_QW2W2_VP | vp_cam);
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- pr_debug("(New HW value: %08x)\n",
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- in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
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+ out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam);
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}
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static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
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