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@@ -1854,7 +1854,8 @@ i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
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else
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else
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hw_link_info->lse_enable = false;
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hw_link_info->lse_enable = false;
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- if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
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+ if ((hw->mac.type == I40E_MAC_XL710) &&
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+ (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
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hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
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hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
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hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
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hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
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@@ -2168,6 +2169,40 @@ enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
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return status;
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return status;
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}
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}
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+/**
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+ * i40e_aq_set_vsi_bc_promisc_on_vlan
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+ * @hw: pointer to the hw struct
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+ * @seid: vsi number
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+ * @enable: set broadcast promiscuous enable/disable for a given VLAN
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+ * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
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+ * @cmd_details: pointer to command details structure or NULL
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+ **/
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+i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
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+ u16 seid, bool enable, u16 vid,
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+ struct i40e_asq_cmd_details *cmd_details)
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+{
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+ struct i40e_aq_desc desc;
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+ struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
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+ (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
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+ i40e_status status;
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+ u16 flags = 0;
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+
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+ i40e_fill_default_direct_cmd_desc(&desc,
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+ i40e_aqc_opc_set_vsi_promiscuous_modes);
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+
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+ if (enable)
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+ flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
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+
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+ cmd->promiscuous_flags = cpu_to_le16(flags);
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+ cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
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+ cmd->seid = cpu_to_le16(seid);
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+ cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
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+
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+ status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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+
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+ return status;
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+}
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+
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/**
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/**
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* i40e_aq_set_vsi_broadcast
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* i40e_aq_set_vsi_broadcast
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* @hw: pointer to the hw struct
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* @hw: pointer to the hw struct
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@@ -3147,6 +3182,14 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
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break;
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break;
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case I40E_AQ_CAP_ID_MNG_MODE:
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case I40E_AQ_CAP_ID_MNG_MODE:
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p->management_mode = number;
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p->management_mode = number;
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+ if (major_rev > 1) {
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+ p->mng_protocols_over_mctp = logical_id;
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+ i40e_debug(hw, I40E_DEBUG_INIT,
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+ "HW Capability: Protocols over MCTP = %d\n",
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+ p->mng_protocols_over_mctp);
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+ } else {
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+ p->mng_protocols_over_mctp = 0;
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+ }
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break;
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break;
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case I40E_AQ_CAP_ID_NPAR_ACTIVE:
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case I40E_AQ_CAP_ID_NPAR_ACTIVE:
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p->npar_enable = number;
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p->npar_enable = number;
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@@ -4396,7 +4439,92 @@ i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
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}
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}
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/**
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/**
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- * i40e_read_phy_register
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+ * i40e_read_phy_register_clause22
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+ * @hw: pointer to the HW structure
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+ * @reg: register address in the page
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+ * @phy_adr: PHY address on MDIO interface
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+ * @value: PHY register value
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+ *
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+ * Reads specified PHY register value
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+ **/
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+i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
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+ u16 reg, u8 phy_addr, u16 *value)
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+{
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+ i40e_status status = I40E_ERR_TIMEOUT;
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+ u8 port_num = (u8)hw->func_caps.mdio_port_num;
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+ u32 command = 0;
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+ u16 retry = 1000;
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+
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+ command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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+ (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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+ (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
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+ (I40E_MDIO_CLAUSE22_STCODE_MASK) |
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+ (I40E_GLGEN_MSCA_MDICMD_MASK);
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+ wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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+ do {
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+ command = rd32(hw, I40E_GLGEN_MSCA(port_num));
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+ if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
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+ status = 0;
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+ break;
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+ }
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+ udelay(10);
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+ retry--;
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+ } while (retry);
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+
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+ if (status) {
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+ i40e_debug(hw, I40E_DEBUG_PHY,
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+ "PHY: Can't write command to external PHY.\n");
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+ } else {
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+ command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
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+ *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
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+ I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
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+ }
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+
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+ return status;
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+}
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+
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+/**
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+ * i40e_write_phy_register_clause22
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+ * @hw: pointer to the HW structure
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+ * @reg: register address in the page
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+ * @phy_adr: PHY address on MDIO interface
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+ * @value: PHY register value
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+ *
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+ * Writes specified PHY register value
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+ **/
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+i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
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+ u16 reg, u8 phy_addr, u16 value)
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+{
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+ i40e_status status = I40E_ERR_TIMEOUT;
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+ u8 port_num = (u8)hw->func_caps.mdio_port_num;
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+ u32 command = 0;
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+ u16 retry = 1000;
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+
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+ command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
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+ wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
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+
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+ command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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+ (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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+ (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
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+ (I40E_MDIO_CLAUSE22_STCODE_MASK) |
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+ (I40E_GLGEN_MSCA_MDICMD_MASK);
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+
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+ wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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+ do {
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+ command = rd32(hw, I40E_GLGEN_MSCA(port_num));
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+ if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
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+ status = 0;
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+ break;
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+ }
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+ udelay(10);
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+ retry--;
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+ } while (retry);
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+
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+ return status;
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+}
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+
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+/**
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+ * i40e_read_phy_register_clause45
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* @hw: pointer to the HW structure
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* @hw: pointer to the HW structure
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* @page: registers page number
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* @page: registers page number
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* @reg: register address in the page
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* @reg: register address in the page
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@@ -4405,9 +4533,8 @@ i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
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*
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*
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* Reads specified PHY register value
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* Reads specified PHY register value
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**/
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**/
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-i40e_status i40e_read_phy_register(struct i40e_hw *hw,
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- u8 page, u16 reg, u8 phy_addr,
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- u16 *value)
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+i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
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+ u8 page, u16 reg, u8 phy_addr, u16 *value)
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{
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{
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i40e_status status = I40E_ERR_TIMEOUT;
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i40e_status status = I40E_ERR_TIMEOUT;
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u32 command = 0;
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u32 command = 0;
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@@ -4417,8 +4544,8 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,
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command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
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command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
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(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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- (I40E_MDIO_OPCODE_ADDRESS) |
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- (I40E_MDIO_STCODE) |
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+ (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
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+ (I40E_MDIO_CLAUSE45_STCODE_MASK) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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@@ -4440,8 +4567,8 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,
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command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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- (I40E_MDIO_OPCODE_READ) |
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- (I40E_MDIO_STCODE) |
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+ (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
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+ (I40E_MDIO_CLAUSE45_STCODE_MASK) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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status = I40E_ERR_TIMEOUT;
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status = I40E_ERR_TIMEOUT;
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@@ -4471,7 +4598,7 @@ phy_read_end:
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}
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}
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/**
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/**
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- * i40e_write_phy_register
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+ * i40e_write_phy_register_clause45
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* @hw: pointer to the HW structure
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* @hw: pointer to the HW structure
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* @page: registers page number
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* @page: registers page number
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* @reg: register address in the page
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* @reg: register address in the page
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@@ -4480,9 +4607,8 @@ phy_read_end:
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*
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*
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* Writes value to specified PHY register
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* Writes value to specified PHY register
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**/
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**/
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-i40e_status i40e_write_phy_register(struct i40e_hw *hw,
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- u8 page, u16 reg, u8 phy_addr,
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- u16 value)
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+i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
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+ u8 page, u16 reg, u8 phy_addr, u16 value)
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{
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{
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i40e_status status = I40E_ERR_TIMEOUT;
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i40e_status status = I40E_ERR_TIMEOUT;
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u32 command = 0;
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u32 command = 0;
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@@ -4492,8 +4618,8 @@ i40e_status i40e_write_phy_register(struct i40e_hw *hw,
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command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
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command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
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(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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- (I40E_MDIO_OPCODE_ADDRESS) |
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- (I40E_MDIO_STCODE) |
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+ (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
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+ (I40E_MDIO_CLAUSE45_STCODE_MASK) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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wr32(hw, I40E_GLGEN_MSCA(port_num), command);
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@@ -4517,8 +4643,8 @@ i40e_status i40e_write_phy_register(struct i40e_hw *hw,
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command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
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- (I40E_MDIO_OPCODE_WRITE) |
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- (I40E_MDIO_STCODE) |
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+ (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
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+ (I40E_MDIO_CLAUSE45_STCODE_MASK) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDICMD_MASK) |
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
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status = I40E_ERR_TIMEOUT;
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status = I40E_ERR_TIMEOUT;
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@@ -4580,14 +4706,16 @@ i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
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for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
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for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
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led_addr++) {
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led_addr++) {
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- status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
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- led_addr, phy_addr, &led_reg);
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+ status = i40e_read_phy_register_clause45(hw,
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+ I40E_PHY_COM_REG_PAGE,
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+ led_addr, phy_addr,
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+ &led_reg);
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if (status)
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if (status)
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goto phy_blinking_end;
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goto phy_blinking_end;
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led_ctl = led_reg;
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led_ctl = led_reg;
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if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
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if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
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led_reg = 0;
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led_reg = 0;
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- status = i40e_write_phy_register(hw,
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+ status = i40e_write_phy_register_clause45(hw,
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I40E_PHY_COM_REG_PAGE,
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I40E_PHY_COM_REG_PAGE,
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led_addr, phy_addr,
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led_addr, phy_addr,
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led_reg);
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led_reg);
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@@ -4599,20 +4727,18 @@ i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
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if (time > 0 && interval > 0) {
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if (time > 0 && interval > 0) {
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for (i = 0; i < time * 1000; i += interval) {
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for (i = 0; i < time * 1000; i += interval) {
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- status = i40e_read_phy_register(hw,
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- I40E_PHY_COM_REG_PAGE,
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- led_addr, phy_addr,
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- &led_reg);
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+ status = i40e_read_phy_register_clause45(hw,
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+ I40E_PHY_COM_REG_PAGE,
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+ led_addr, phy_addr, &led_reg);
|
|
if (status)
|
|
if (status)
|
|
goto restore_config;
|
|
goto restore_config;
|
|
if (led_reg & I40E_PHY_LED_MANUAL_ON)
|
|
if (led_reg & I40E_PHY_LED_MANUAL_ON)
|
|
led_reg = 0;
|
|
led_reg = 0;
|
|
else
|
|
else
|
|
led_reg = I40E_PHY_LED_MANUAL_ON;
|
|
led_reg = I40E_PHY_LED_MANUAL_ON;
|
|
- status = i40e_write_phy_register(hw,
|
|
|
|
- I40E_PHY_COM_REG_PAGE,
|
|
|
|
- led_addr, phy_addr,
|
|
|
|
- led_reg);
|
|
|
|
|
|
+ status = i40e_write_phy_register_clause45(hw,
|
|
|
|
+ I40E_PHY_COM_REG_PAGE,
|
|
|
|
+ led_addr, phy_addr, led_reg);
|
|
if (status)
|
|
if (status)
|
|
goto restore_config;
|
|
goto restore_config;
|
|
msleep(interval);
|
|
msleep(interval);
|
|
@@ -4620,8 +4746,9 @@ i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
|
|
}
|
|
}
|
|
|
|
|
|
restore_config:
|
|
restore_config:
|
|
- status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
|
|
|
|
- phy_addr, led_ctl);
|
|
|
|
|
|
+ status = i40e_write_phy_register_clause45(hw,
|
|
|
|
+ I40E_PHY_COM_REG_PAGE,
|
|
|
|
+ led_addr, phy_addr, led_ctl);
|
|
|
|
|
|
phy_blinking_end:
|
|
phy_blinking_end:
|
|
return status;
|
|
return status;
|
|
@@ -4652,8 +4779,10 @@ i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
|
|
|
|
|
|
for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
|
|
for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
|
|
temp_addr++) {
|
|
temp_addr++) {
|
|
- status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
|
|
|
|
- temp_addr, phy_addr, ®_val);
|
|
|
|
|
|
+ status = i40e_read_phy_register_clause45(hw,
|
|
|
|
+ I40E_PHY_COM_REG_PAGE,
|
|
|
|
+ temp_addr, phy_addr,
|
|
|
|
+ ®_val);
|
|
if (status)
|
|
if (status)
|
|
return status;
|
|
return status;
|
|
*val = reg_val;
|
|
*val = reg_val;
|
|
@@ -4686,41 +4815,42 @@ i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
|
|
i = rd32(hw, I40E_PFGEN_PORTNUM);
|
|
i = rd32(hw, I40E_PFGEN_PORTNUM);
|
|
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
|
|
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
|
|
phy_addr = i40e_get_phy_address(hw, port_num);
|
|
phy_addr = i40e_get_phy_address(hw, port_num);
|
|
-
|
|
|
|
- status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
|
|
|
|
- phy_addr, &led_reg);
|
|
|
|
|
|
+ status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
|
|
|
|
+ led_addr, phy_addr, &led_reg);
|
|
if (status)
|
|
if (status)
|
|
return status;
|
|
return status;
|
|
led_ctl = led_reg;
|
|
led_ctl = led_reg;
|
|
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
|
|
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
|
|
led_reg = 0;
|
|
led_reg = 0;
|
|
- status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
|
|
|
|
- led_addr, phy_addr, led_reg);
|
|
|
|
|
|
+ status = i40e_write_phy_register_clause45(hw,
|
|
|
|
+ I40E_PHY_COM_REG_PAGE,
|
|
|
|
+ led_addr, phy_addr,
|
|
|
|
+ led_reg);
|
|
if (status)
|
|
if (status)
|
|
return status;
|
|
return status;
|
|
}
|
|
}
|
|
- status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
|
|
|
|
- led_addr, phy_addr, &led_reg);
|
|
|
|
|
|
+ status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
|
|
|
|
+ led_addr, phy_addr, &led_reg);
|
|
if (status)
|
|
if (status)
|
|
goto restore_config;
|
|
goto restore_config;
|
|
if (on)
|
|
if (on)
|
|
led_reg = I40E_PHY_LED_MANUAL_ON;
|
|
led_reg = I40E_PHY_LED_MANUAL_ON;
|
|
else
|
|
else
|
|
led_reg = 0;
|
|
led_reg = 0;
|
|
- status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
|
|
|
|
- led_addr, phy_addr, led_reg);
|
|
|
|
|
|
+ status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
|
|
|
|
+ led_addr, phy_addr, led_reg);
|
|
if (status)
|
|
if (status)
|
|
goto restore_config;
|
|
goto restore_config;
|
|
if (mode & I40E_PHY_LED_MODE_ORIG) {
|
|
if (mode & I40E_PHY_LED_MODE_ORIG) {
|
|
led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
|
|
led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
|
|
- status = i40e_write_phy_register(hw,
|
|
|
|
|
|
+ status = i40e_write_phy_register_clause45(hw,
|
|
I40E_PHY_COM_REG_PAGE,
|
|
I40E_PHY_COM_REG_PAGE,
|
|
led_addr, phy_addr, led_ctl);
|
|
led_addr, phy_addr, led_ctl);
|
|
}
|
|
}
|
|
return status;
|
|
return status;
|
|
restore_config:
|
|
restore_config:
|
|
- status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
|
|
|
|
- phy_addr, led_ctl);
|
|
|
|
|
|
+ status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
|
|
|
|
+ led_addr, phy_addr, led_ctl);
|
|
return status;
|
|
return status;
|
|
}
|
|
}
|
|
|
|
|