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@@ -174,6 +174,8 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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uint32_t i;
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+ struct cgs_system_info sys_info = {0};
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+ int result;
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cz_hwmgr->gfx_ramp_step = 256*25/100;
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@@ -251,6 +253,17 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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PHM_PlatformCaps_UVDPowerGating);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_VCEPowerGating);
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+ sys_info.size = sizeof(struct cgs_system_info);
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+ sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
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+ result = cgs_query_system_info(hwmgr->device, &sys_info);
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+ if (!result) {
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+ if (sys_info.value & AMD_PG_SUPPORT_UVD)
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+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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+ PHM_PlatformCaps_UVDPowerGating);
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+ if (sys_info.value & AMD_PG_SUPPORT_VCE)
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+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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+ PHM_PlatformCaps_VCEPowerGating);
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+ }
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return 0;
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}
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