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@@ -14,6 +14,9 @@
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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+#include <linux/syscore_ops.h>
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define IRQS_PER_BANK 32
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@@ -23,29 +26,69 @@ struct stm32_exti_bank {
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u32 rtsr_ofst;
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u32 ftsr_ofst;
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u32 swier_ofst;
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- u32 pr_ofst;
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+ u32 rpr_ofst;
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+ u32 fpr_ofst;
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+};
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+
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+#define UNDEF_REG ~0
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+
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+struct stm32_desc_irq {
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+ u32 exti;
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+ u32 irq_parent;
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+};
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+
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+struct stm32_exti_drv_data {
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+ const struct stm32_exti_bank **exti_banks;
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+ const struct stm32_desc_irq *desc_irqs;
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+ u32 bank_nr;
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+ u32 irq_nr;
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+};
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+
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+struct stm32_exti_chip_data {
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+ struct stm32_exti_host_data *host_data;
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+ const struct stm32_exti_bank *reg_bank;
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+ struct raw_spinlock rlock;
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+ u32 wake_active;
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+ u32 mask_cache;
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+ u32 rtsr_cache;
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+ u32 ftsr_cache;
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};
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+struct stm32_exti_host_data {
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+ void __iomem *base;
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+ struct stm32_exti_chip_data *chips_data;
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+ const struct stm32_exti_drv_data *drv_data;
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+};
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+
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+static struct stm32_exti_host_data *stm32_host_data;
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+
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static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
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.imr_ofst = 0x00,
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.emr_ofst = 0x04,
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.rtsr_ofst = 0x08,
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.ftsr_ofst = 0x0C,
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.swier_ofst = 0x10,
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- .pr_ofst = 0x14,
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+ .rpr_ofst = 0x14,
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+ .fpr_ofst = UNDEF_REG,
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};
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static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
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&stm32f4xx_exti_b1,
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};
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+static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
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+ .exti_banks = stm32f4xx_exti_banks,
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+ .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
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+};
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+
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static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
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.imr_ofst = 0x80,
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.emr_ofst = 0x84,
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.rtsr_ofst = 0x00,
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.ftsr_ofst = 0x04,
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.swier_ofst = 0x08,
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- .pr_ofst = 0x88,
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+ .rpr_ofst = 0x88,
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+ .fpr_ofst = UNDEF_REG,
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};
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static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
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@@ -54,7 +97,8 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
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.rtsr_ofst = 0x20,
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.ftsr_ofst = 0x24,
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.swier_ofst = 0x28,
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- .pr_ofst = 0x98,
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+ .rpr_ofst = 0x98,
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+ .fpr_ofst = UNDEF_REG,
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};
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static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
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@@ -63,7 +107,8 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
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.rtsr_ofst = 0x40,
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.ftsr_ofst = 0x44,
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.swier_ofst = 0x48,
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- .pr_ofst = 0xA8,
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+ .rpr_ofst = 0xA8,
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+ .fpr_ofst = UNDEF_REG,
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};
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static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
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@@ -72,18 +117,105 @@ static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
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&stm32h7xx_exti_b3,
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};
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-static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
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+static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
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+ .exti_banks = stm32h7xx_exti_banks,
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+ .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
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+};
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+
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+static const struct stm32_exti_bank stm32mp1_exti_b1 = {
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+ .imr_ofst = 0x80,
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+ .emr_ofst = 0x84,
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+ .rtsr_ofst = 0x00,
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+ .ftsr_ofst = 0x04,
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+ .swier_ofst = 0x08,
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+ .rpr_ofst = 0x0C,
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+ .fpr_ofst = 0x10,
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+};
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+
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+static const struct stm32_exti_bank stm32mp1_exti_b2 = {
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+ .imr_ofst = 0x90,
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+ .emr_ofst = 0x94,
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+ .rtsr_ofst = 0x20,
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+ .ftsr_ofst = 0x24,
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+ .swier_ofst = 0x28,
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+ .rpr_ofst = 0x2C,
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+ .fpr_ofst = 0x30,
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+};
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+
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+static const struct stm32_exti_bank stm32mp1_exti_b3 = {
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+ .imr_ofst = 0xA0,
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+ .emr_ofst = 0xA4,
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+ .rtsr_ofst = 0x40,
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+ .ftsr_ofst = 0x44,
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+ .swier_ofst = 0x48,
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+ .rpr_ofst = 0x4C,
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+ .fpr_ofst = 0x50,
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+};
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+
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+static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
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+ &stm32mp1_exti_b1,
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+ &stm32mp1_exti_b2,
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+ &stm32mp1_exti_b3,
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+};
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+
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+static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
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+ { .exti = 1, .irq_parent = 7 },
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+ { .exti = 2, .irq_parent = 8 },
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+ { .exti = 3, .irq_parent = 9 },
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+ { .exti = 4, .irq_parent = 10 },
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+ { .exti = 5, .irq_parent = 23 },
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+ { .exti = 6, .irq_parent = 64 },
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+ { .exti = 7, .irq_parent = 65 },
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+ { .exti = 8, .irq_parent = 66 },
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+ { .exti = 9, .irq_parent = 67 },
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+ { .exti = 10, .irq_parent = 40 },
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+ { .exti = 11, .irq_parent = 42 },
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+ { .exti = 12, .irq_parent = 76 },
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+ { .exti = 13, .irq_parent = 77 },
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+ { .exti = 14, .irq_parent = 121 },
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+ { .exti = 15, .irq_parent = 127 },
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+ { .exti = 16, .irq_parent = 1 },
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+ { .exti = 65, .irq_parent = 144 },
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+ { .exti = 68, .irq_parent = 143 },
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+ { .exti = 73, .irq_parent = 129 },
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+};
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+
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+static const struct stm32_exti_drv_data stm32mp1_drv_data = {
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+ .exti_banks = stm32mp1_exti_banks,
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+ .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
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+ .desc_irqs = stm32mp1_desc_irq,
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+ .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
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+};
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+
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+static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data,
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+ irq_hw_number_t hwirq)
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{
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- const struct stm32_exti_bank *stm32_bank = gc->private;
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+ const struct stm32_desc_irq *desc_irq;
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+ int i;
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- return irq_reg_readl(gc, stm32_bank->pr_ofst);
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+ if (!drv_data->desc_irqs)
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+ return -EINVAL;
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+
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+ for (i = 0; i < drv_data->irq_nr; i++) {
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+ desc_irq = &drv_data->desc_irqs[i];
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+ if (desc_irq->exti == hwirq)
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+ return desc_irq->irq_parent;
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+ }
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+
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+ return -EINVAL;
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}
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-static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask)
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+static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
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{
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- const struct stm32_exti_bank *stm32_bank = gc->private;
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+ struct stm32_exti_chip_data *chip_data = gc->private;
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+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
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+ unsigned long pending;
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+
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+ pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
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+ if (stm32_bank->fpr_ofst != UNDEF_REG)
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+ pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
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- irq_reg_writel(gc, mask, stm32_bank->pr_ofst);
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+ return pending;
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}
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static void stm32_irq_handler(struct irq_desc *desc)
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@@ -92,7 +224,6 @@ static void stm32_irq_handler(struct irq_desc *desc)
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int virq, nbanks = domain->gc->num_chips;
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struct irq_chip_generic *gc;
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- const struct stm32_exti_bank *stm32_bank;
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unsigned long pending;
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int n, i, irq_base = 0;
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@@ -100,13 +231,11 @@ static void stm32_irq_handler(struct irq_desc *desc)
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for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
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gc = irq_get_domain_generic_chip(domain, irq_base);
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- stm32_bank = gc->private;
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while ((pending = stm32_exti_pending(gc))) {
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for_each_set_bit(n, &pending, IRQS_PER_BANK) {
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virq = irq_find_mapping(domain, irq_base + n);
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generic_handle_irq(virq);
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- stm32_exti_irq_ack(gc, BIT(n));
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}
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}
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}
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@@ -114,36 +243,50 @@ static void stm32_irq_handler(struct irq_desc *desc)
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chained_irq_exit(chip, desc);
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}
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-static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
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+static int stm32_exti_set_type(struct irq_data *d,
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+ unsigned int type, u32 *rtsr, u32 *ftsr)
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{
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- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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- const struct stm32_exti_bank *stm32_bank = gc->private;
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- int pin = data->hwirq % IRQS_PER_BANK;
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- u32 rtsr, ftsr;
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-
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- irq_gc_lock(gc);
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-
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- rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
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- ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
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+ u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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- rtsr |= BIT(pin);
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- ftsr &= ~BIT(pin);
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+ *rtsr |= mask;
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+ *ftsr &= ~mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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- rtsr &= ~BIT(pin);
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- ftsr |= BIT(pin);
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+ *rtsr &= ~mask;
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+ *ftsr |= mask;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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- rtsr |= BIT(pin);
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- ftsr |= BIT(pin);
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+ *rtsr |= mask;
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+ *ftsr |= mask;
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break;
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default:
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- irq_gc_unlock(gc);
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return -EINVAL;
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}
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+ return 0;
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+}
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+
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+static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
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+{
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+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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+ struct stm32_exti_chip_data *chip_data = gc->private;
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+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
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+ u32 rtsr, ftsr;
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+ int err;
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+
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+ irq_gc_lock(gc);
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+
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+ rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
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+ ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
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+
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+ err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
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+ if (err) {
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+ irq_gc_unlock(gc);
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+ return err;
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+ }
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+
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irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
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irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
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@@ -152,40 +295,59 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
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return 0;
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}
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-static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
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+static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
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+ u32 wake_active)
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{
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- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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- const struct stm32_exti_bank *stm32_bank = gc->private;
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- int pin = data->hwirq % IRQS_PER_BANK;
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- u32 imr;
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+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
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+ void __iomem *base = chip_data->host_data->base;
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- irq_gc_lock(gc);
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+ /* save rtsr, ftsr registers */
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+ chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
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+ chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
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- imr = irq_reg_readl(gc, stm32_bank->imr_ofst);
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- if (on)
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- imr |= BIT(pin);
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- else
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- imr &= ~BIT(pin);
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- irq_reg_writel(gc, imr, stm32_bank->imr_ofst);
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+ writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
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+}
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+
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+static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
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+ u32 mask_cache)
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+{
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+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
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+ void __iomem *base = chip_data->host_data->base;
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+
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+ /* restore rtsr, ftsr, registers */
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+ writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
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+ writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
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+ writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
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+}
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+
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+static void stm32_irq_suspend(struct irq_chip_generic *gc)
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+{
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+ struct stm32_exti_chip_data *chip_data = gc->private;
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+
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+ irq_gc_lock(gc);
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+ stm32_chip_suspend(chip_data, gc->wake_active);
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irq_gc_unlock(gc);
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+}
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- return 0;
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+static void stm32_irq_resume(struct irq_chip_generic *gc)
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+{
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+ struct stm32_exti_chip_data *chip_data = gc->private;
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+
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+ irq_gc_lock(gc);
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+ stm32_chip_resume(chip_data, gc->mask_cache);
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+ irq_gc_unlock(gc);
|
|
|
}
|
|
|
|
|
|
static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
|
|
|
unsigned int nr_irqs, void *data)
|
|
|
{
|
|
|
- struct irq_chip_generic *gc;
|
|
|
struct irq_fwspec *fwspec = data;
|
|
|
irq_hw_number_t hwirq;
|
|
|
|
|
|
hwirq = fwspec->param[0];
|
|
|
- gc = irq_get_domain_generic_chip(d, hwirq);
|
|
|
|
|
|
irq_map_generic_chip(d, virq, hwirq);
|
|
|
- irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
|
|
|
- handle_simple_irq, NULL, NULL);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
@@ -198,30 +360,318 @@ static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
|
|
|
irq_domain_reset_irq_data(data);
|
|
|
}
|
|
|
|
|
|
-struct irq_domain_ops irq_exti_domain_ops = {
|
|
|
+static const struct irq_domain_ops irq_exti_domain_ops = {
|
|
|
.map = irq_map_generic_chip,
|
|
|
- .xlate = irq_domain_xlate_onetwocell,
|
|
|
.alloc = stm32_exti_alloc,
|
|
|
.free = stm32_exti_free,
|
|
|
};
|
|
|
|
|
|
-static int
|
|
|
-__init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
|
|
|
- int bank_nr, struct device_node *node)
|
|
|
+static void stm32_irq_ack(struct irq_data *d)
|
|
|
+{
|
|
|
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
|
|
+ struct stm32_exti_chip_data *chip_data = gc->private;
|
|
|
+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
|
|
|
+
|
|
|
+ irq_gc_lock(gc);
|
|
|
+
|
|
|
+ irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
|
|
|
+ if (stm32_bank->fpr_ofst != UNDEF_REG)
|
|
|
+ irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
|
|
|
+
|
|
|
+ irq_gc_unlock(gc);
|
|
|
+}
|
|
|
+
|
|
|
+static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
|
|
|
{
|
|
|
+ struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
|
|
|
+ void __iomem *base = chip_data->host_data->base;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ val = readl_relaxed(base + reg);
|
|
|
+ val |= BIT(d->hwirq % IRQS_PER_BANK);
|
|
|
+ writel_relaxed(val, base + reg);
|
|
|
+
|
|
|
+ return val;
|
|
|
+}
|
|
|
+
|
|
|
+static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
|
|
|
+{
|
|
|
+ struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
|
|
|
+ void __iomem *base = chip_data->host_data->base;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ val = readl_relaxed(base + reg);
|
|
|
+ val &= ~BIT(d->hwirq % IRQS_PER_BANK);
|
|
|
+ writel_relaxed(val, base + reg);
|
|
|
+
|
|
|
+ return val;
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32_exti_h_eoi(struct irq_data *d)
|
|
|
+{
|
|
|
+ struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
|
|
|
+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
|
|
|
+
|
|
|
+ raw_spin_lock(&chip_data->rlock);
|
|
|
+
|
|
|
+ stm32_exti_set_bit(d, stm32_bank->rpr_ofst);
|
|
|
+ if (stm32_bank->fpr_ofst != UNDEF_REG)
|
|
|
+ stm32_exti_set_bit(d, stm32_bank->fpr_ofst);
|
|
|
+
|
|
|
+ raw_spin_unlock(&chip_data->rlock);
|
|
|
+
|
|
|
+ if (d->parent_data->chip)
|
|
|
+ irq_chip_eoi_parent(d);
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32_exti_h_mask(struct irq_data *d)
|
|
|
+{
|
|
|
+ struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
|
|
|
+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
|
|
|
+
|
|
|
+ raw_spin_lock(&chip_data->rlock);
|
|
|
+ chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
|
|
|
+ raw_spin_unlock(&chip_data->rlock);
|
|
|
+
|
|
|
+ if (d->parent_data->chip)
|
|
|
+ irq_chip_mask_parent(d);
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32_exti_h_unmask(struct irq_data *d)
|
|
|
+{
|
|
|
+ struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
|
|
|
+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
|
|
|
+
|
|
|
+ raw_spin_lock(&chip_data->rlock);
|
|
|
+ chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
|
|
|
+ raw_spin_unlock(&chip_data->rlock);
|
|
|
+
|
|
|
+ if (d->parent_data->chip)
|
|
|
+ irq_chip_unmask_parent(d);
|
|
|
+}
|
|
|
+
|
|
|
+static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
|
|
|
+{
|
|
|
+ struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
|
|
|
+ const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
|
|
|
+ void __iomem *base = chip_data->host_data->base;
|
|
|
+ u32 rtsr, ftsr;
|
|
|
+ int err;
|
|
|
+
|
|
|
+ raw_spin_lock(&chip_data->rlock);
|
|
|
+ rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
|
|
|
+ ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
|
|
|
+
|
|
|
+ err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
|
|
|
+ if (err) {
|
|
|
+ raw_spin_unlock(&chip_data->rlock);
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
|
|
|
+ writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
|
|
|
+ raw_spin_unlock(&chip_data->rlock);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
|
|
|
+{
|
|
|
+ struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
|
|
|
+ u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
|
|
|
+
|
|
|
+ raw_spin_lock(&chip_data->rlock);
|
|
|
+
|
|
|
+ if (on)
|
|
|
+ chip_data->wake_active |= mask;
|
|
|
+ else
|
|
|
+ chip_data->wake_active &= ~mask;
|
|
|
+
|
|
|
+ raw_spin_unlock(&chip_data->rlock);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int stm32_exti_h_set_affinity(struct irq_data *d,
|
|
|
+ const struct cpumask *dest, bool force)
|
|
|
+{
|
|
|
+ if (d->parent_data->chip)
|
|
|
+ return irq_chip_set_affinity_parent(d, dest, force);
|
|
|
+
|
|
|
+ return -EINVAL;
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef CONFIG_PM
|
|
|
+static int stm32_exti_h_suspend(void)
|
|
|
+{
|
|
|
+ struct stm32_exti_chip_data *chip_data;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
|
|
|
+ chip_data = &stm32_host_data->chips_data[i];
|
|
|
+ raw_spin_lock(&chip_data->rlock);
|
|
|
+ stm32_chip_suspend(chip_data, chip_data->wake_active);
|
|
|
+ raw_spin_unlock(&chip_data->rlock);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32_exti_h_resume(void)
|
|
|
+{
|
|
|
+ struct stm32_exti_chip_data *chip_data;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
|
|
|
+ chip_data = &stm32_host_data->chips_data[i];
|
|
|
+ raw_spin_lock(&chip_data->rlock);
|
|
|
+ stm32_chip_resume(chip_data, chip_data->mask_cache);
|
|
|
+ raw_spin_unlock(&chip_data->rlock);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static struct syscore_ops stm32_exti_h_syscore_ops = {
|
|
|
+ .suspend = stm32_exti_h_suspend,
|
|
|
+ .resume = stm32_exti_h_resume,
|
|
|
+};
|
|
|
+
|
|
|
+static void stm32_exti_h_syscore_init(void)
|
|
|
+{
|
|
|
+ register_syscore_ops(&stm32_exti_h_syscore_ops);
|
|
|
+}
|
|
|
+#else
|
|
|
+static inline void stm32_exti_h_syscore_init(void) {}
|
|
|
+#endif
|
|
|
+
|
|
|
+static struct irq_chip stm32_exti_h_chip = {
|
|
|
+ .name = "stm32-exti-h",
|
|
|
+ .irq_eoi = stm32_exti_h_eoi,
|
|
|
+ .irq_mask = stm32_exti_h_mask,
|
|
|
+ .irq_unmask = stm32_exti_h_unmask,
|
|
|
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
|
|
|
+ .irq_set_type = stm32_exti_h_set_type,
|
|
|
+ .irq_set_wake = stm32_exti_h_set_wake,
|
|
|
+ .flags = IRQCHIP_MASK_ON_SUSPEND,
|
|
|
+#ifdef CONFIG_SMP
|
|
|
+ .irq_set_affinity = stm32_exti_h_set_affinity,
|
|
|
+#endif
|
|
|
+};
|
|
|
+
|
|
|
+static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
|
|
|
+ unsigned int virq,
|
|
|
+ unsigned int nr_irqs, void *data)
|
|
|
+{
|
|
|
+ struct stm32_exti_host_data *host_data = dm->host_data;
|
|
|
+ struct stm32_exti_chip_data *chip_data;
|
|
|
+ struct irq_fwspec *fwspec = data;
|
|
|
+ struct irq_fwspec p_fwspec;
|
|
|
+ irq_hw_number_t hwirq;
|
|
|
+ int p_irq, bank;
|
|
|
+
|
|
|
+ hwirq = fwspec->param[0];
|
|
|
+ bank = hwirq / IRQS_PER_BANK;
|
|
|
+ chip_data = &host_data->chips_data[bank];
|
|
|
+
|
|
|
+ irq_domain_set_hwirq_and_chip(dm, virq, hwirq,
|
|
|
+ &stm32_exti_h_chip, chip_data);
|
|
|
+
|
|
|
+ p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq);
|
|
|
+ if (p_irq >= 0) {
|
|
|
+ p_fwspec.fwnode = dm->parent->fwnode;
|
|
|
+ p_fwspec.param_count = 3;
|
|
|
+ p_fwspec.param[0] = GIC_SPI;
|
|
|
+ p_fwspec.param[1] = p_irq;
|
|
|
+ p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
|
|
|
+
|
|
|
+ return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct
|
|
|
+stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
|
|
|
+ struct device_node *node)
|
|
|
+{
|
|
|
+ struct stm32_exti_host_data *host_data;
|
|
|
+
|
|
|
+ host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
|
|
|
+ if (!host_data)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ host_data->drv_data = dd;
|
|
|
+ host_data->chips_data = kcalloc(dd->bank_nr,
|
|
|
+ sizeof(struct stm32_exti_chip_data),
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!host_data->chips_data)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ host_data->base = of_iomap(node, 0);
|
|
|
+ if (!host_data->base) {
|
|
|
+ pr_err("%pOF: Unable to map registers\n", node);
|
|
|
+ return NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ stm32_host_data = host_data;
|
|
|
+
|
|
|
+ return host_data;
|
|
|
+}
|
|
|
+
|
|
|
+static struct
|
|
|
+stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
|
|
|
+ u32 bank_idx,
|
|
|
+ struct device_node *node)
|
|
|
+{
|
|
|
+ const struct stm32_exti_bank *stm32_bank;
|
|
|
+ struct stm32_exti_chip_data *chip_data;
|
|
|
+ void __iomem *base = h_data->base;
|
|
|
+ u32 irqs_mask;
|
|
|
+
|
|
|
+ stm32_bank = h_data->drv_data->exti_banks[bank_idx];
|
|
|
+ chip_data = &h_data->chips_data[bank_idx];
|
|
|
+ chip_data->host_data = h_data;
|
|
|
+ chip_data->reg_bank = stm32_bank;
|
|
|
+
|
|
|
+ raw_spin_lock_init(&chip_data->rlock);
|
|
|
+
|
|
|
+ /* Determine number of irqs supported */
|
|
|
+ writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
|
|
|
+ irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * This IP has no reset, so after hot reboot we should
|
|
|
+ * clear registers to avoid residue
|
|
|
+ */
|
|
|
+ writel_relaxed(0, base + stm32_bank->imr_ofst);
|
|
|
+ writel_relaxed(0, base + stm32_bank->emr_ofst);
|
|
|
+ writel_relaxed(0, base + stm32_bank->rtsr_ofst);
|
|
|
+ writel_relaxed(0, base + stm32_bank->ftsr_ofst);
|
|
|
+ writel_relaxed(~0UL, base + stm32_bank->rpr_ofst);
|
|
|
+ if (stm32_bank->fpr_ofst != UNDEF_REG)
|
|
|
+ writel_relaxed(~0UL, base + stm32_bank->fpr_ofst);
|
|
|
+
|
|
|
+ pr_info("%s: bank%d, External IRQs available:%#x\n",
|
|
|
+ node->full_name, bank_idx, irqs_mask);
|
|
|
+
|
|
|
+ return chip_data;
|
|
|
+}
|
|
|
+
|
|
|
+static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
|
|
|
+ struct device_node *node)
|
|
|
+{
|
|
|
+ struct stm32_exti_host_data *host_data;
|
|
|
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
|
|
- int nr_irqs, nr_exti, ret, i;
|
|
|
+ int nr_irqs, ret, i;
|
|
|
struct irq_chip_generic *gc;
|
|
|
struct irq_domain *domain;
|
|
|
- void *base;
|
|
|
|
|
|
- base = of_iomap(node, 0);
|
|
|
- if (!base) {
|
|
|
- pr_err("%pOF: Unable to map registers\n", node);
|
|
|
- return -ENOMEM;
|
|
|
+ host_data = stm32_exti_host_init(drv_data, node);
|
|
|
+ if (!host_data) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto out_free_mem;
|
|
|
}
|
|
|
|
|
|
- domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
|
|
|
+ domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
|
|
|
&irq_exti_domain_ops, NULL);
|
|
|
if (!domain) {
|
|
|
pr_err("%s: Could not register interrupt domain.\n",
|
|
|
@@ -234,44 +684,32 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
|
|
|
handle_edge_irq, clr, 0, 0);
|
|
|
if (ret) {
|
|
|
pr_err("%pOF: Could not allocate generic interrupt chip.\n",
|
|
|
- node);
|
|
|
+ node);
|
|
|
goto out_free_domain;
|
|
|
}
|
|
|
|
|
|
- for (i = 0; i < bank_nr; i++) {
|
|
|
- const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
|
|
|
- u32 irqs_mask;
|
|
|
+ for (i = 0; i < drv_data->bank_nr; i++) {
|
|
|
+ const struct stm32_exti_bank *stm32_bank;
|
|
|
+ struct stm32_exti_chip_data *chip_data;
|
|
|
+
|
|
|
+ stm32_bank = drv_data->exti_banks[i];
|
|
|
+ chip_data = stm32_exti_chip_init(host_data, i, node);
|
|
|
|
|
|
gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
|
|
|
|
|
|
- gc->reg_base = base;
|
|
|
+ gc->reg_base = host_data->base;
|
|
|
gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
|
|
|
- gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
|
|
|
+ gc->chip_types->chip.irq_ack = stm32_irq_ack;
|
|
|
gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
|
|
|
gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
|
|
|
gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
|
|
|
- gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
|
|
|
- gc->chip_types->regs.ack = stm32_bank->pr_ofst;
|
|
|
+ gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
|
|
|
+ gc->suspend = stm32_irq_suspend;
|
|
|
+ gc->resume = stm32_irq_resume;
|
|
|
+ gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
|
|
|
+
|
|
|
gc->chip_types->regs.mask = stm32_bank->imr_ofst;
|
|
|
- gc->private = (void *)stm32_bank;
|
|
|
-
|
|
|
- /* Determine number of irqs supported */
|
|
|
- writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
|
|
|
- irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
|
|
|
- nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
|
|
|
-
|
|
|
- /*
|
|
|
- * This IP has no reset, so after hot reboot we should
|
|
|
- * clear registers to avoid residue
|
|
|
- */
|
|
|
- writel_relaxed(0, base + stm32_bank->imr_ofst);
|
|
|
- writel_relaxed(0, base + stm32_bank->emr_ofst);
|
|
|
- writel_relaxed(0, base + stm32_bank->rtsr_ofst);
|
|
|
- writel_relaxed(0, base + stm32_bank->ftsr_ofst);
|
|
|
- writel_relaxed(~0UL, base + stm32_bank->pr_ofst);
|
|
|
-
|
|
|
- pr_info("%s: bank%d, External IRQs available:%#x\n",
|
|
|
- node->full_name, i, irqs_mask);
|
|
|
+ gc->private = (void *)chip_data;
|
|
|
}
|
|
|
|
|
|
nr_irqs = of_irq_count(node);
|
|
|
@@ -287,15 +725,69 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
|
|
|
out_free_domain:
|
|
|
irq_domain_remove(domain);
|
|
|
out_unmap:
|
|
|
- iounmap(base);
|
|
|
+ iounmap(host_data->base);
|
|
|
+out_free_mem:
|
|
|
+ kfree(host_data->chips_data);
|
|
|
+ kfree(host_data);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct irq_domain_ops stm32_exti_h_domain_ops = {
|
|
|
+ .alloc = stm32_exti_h_domain_alloc,
|
|
|
+ .free = irq_domain_free_irqs_common,
|
|
|
+};
|
|
|
+
|
|
|
+static int
|
|
|
+__init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data,
|
|
|
+ struct device_node *node,
|
|
|
+ struct device_node *parent)
|
|
|
+{
|
|
|
+ struct irq_domain *parent_domain, *domain;
|
|
|
+ struct stm32_exti_host_data *host_data;
|
|
|
+ int ret, i;
|
|
|
+
|
|
|
+ parent_domain = irq_find_host(parent);
|
|
|
+ if (!parent_domain) {
|
|
|
+ pr_err("interrupt-parent not found\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ host_data = stm32_exti_host_init(drv_data, node);
|
|
|
+ if (!host_data) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto out_free_mem;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < drv_data->bank_nr; i++)
|
|
|
+ stm32_exti_chip_init(host_data, i, node);
|
|
|
+
|
|
|
+ domain = irq_domain_add_hierarchy(parent_domain, 0,
|
|
|
+ drv_data->bank_nr * IRQS_PER_BANK,
|
|
|
+ node, &stm32_exti_h_domain_ops,
|
|
|
+ host_data);
|
|
|
+
|
|
|
+ if (!domain) {
|
|
|
+ pr_err("%s: Could not register exti domain.\n", node->name);
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto out_unmap;
|
|
|
+ }
|
|
|
+
|
|
|
+ stm32_exti_h_syscore_init();
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+out_unmap:
|
|
|
+ iounmap(host_data->base);
|
|
|
+out_free_mem:
|
|
|
+ kfree(host_data->chips_data);
|
|
|
+ kfree(host_data);
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
static int __init stm32f4_exti_of_init(struct device_node *np,
|
|
|
struct device_node *parent)
|
|
|
{
|
|
|
- return stm32_exti_init(stm32f4xx_exti_banks,
|
|
|
- ARRAY_SIZE(stm32f4xx_exti_banks), np);
|
|
|
+ return stm32_exti_init(&stm32f4xx_drv_data, np);
|
|
|
}
|
|
|
|
|
|
IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
|
|
|
@@ -303,8 +795,15 @@ IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
|
|
|
static int __init stm32h7_exti_of_init(struct device_node *np,
|
|
|
struct device_node *parent)
|
|
|
{
|
|
|
- return stm32_exti_init(stm32h7xx_exti_banks,
|
|
|
- ARRAY_SIZE(stm32h7xx_exti_banks), np);
|
|
|
+ return stm32_exti_init(&stm32h7xx_drv_data, np);
|
|
|
}
|
|
|
|
|
|
IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
|
|
|
+
|
|
|
+static int __init stm32mp1_exti_of_init(struct device_node *np,
|
|
|
+ struct device_node *parent)
|
|
|
+{
|
|
|
+ return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent);
|
|
|
+}
|
|
|
+
|
|
|
+IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init);
|
Linus Torvalds