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@@ -3702,7 +3702,8 @@ static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
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static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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struct link_params *params,
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struct link_params *params,
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struct link_vars *vars) {
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struct link_vars *vars) {
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- u16 lane, i, cl72_ctrl, an_adv = 0;
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+ u16 lane, i, cl72_ctrl, an_adv = 0, val;
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+ u32 wc_lane_config;
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struct bnx2x *bp = params->bp;
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struct bnx2x *bp = params->bp;
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static struct bnx2x_reg_set reg_set[] = {
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static struct bnx2x_reg_set reg_set[] = {
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
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@@ -3821,15 +3822,27 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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/* Enable Auto-Detect to support 1G over CL37 as well */
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/* Enable Auto-Detect to support 1G over CL37 as well */
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
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-
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+ wc_lane_config = REG_RD(bp, params->shmem_base +
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+ offsetof(struct shmem_region, dev_info.
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+ shared_hw_config.wc_lane_config));
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+ bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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+ MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
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/* Force cl48 sync_status LOW to avoid getting stuck in CL73
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/* Force cl48 sync_status LOW to avoid getting stuck in CL73
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* parallel-detect loop when CL73 and CL37 are enabled.
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* parallel-detect loop when CL73 and CL37 are enabled.
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*/
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*/
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- CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
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- MDIO_AER_BLOCK_AER_REG, 0);
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+ val |= 1 << 11;
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+
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+ /* Restore Polarity settings in case it was run over by
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+ * previous link owner
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+ */
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+ if (wc_lane_config &
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+ (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
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+ val |= 3 << 2;
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+ else
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+ val &= ~(3 << 2);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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- MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
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- bnx2x_set_aer_mmd(params, phy);
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+ MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
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+ val);
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bnx2x_disable_kr2(params, vars, phy);
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bnx2x_disable_kr2(params, vars, phy);
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}
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}
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