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@@ -70,6 +70,11 @@
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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#define PCIE_ATU_UPPER_TARGET 0x91C
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+/* PCIe Port Logic registers */
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+#define PLR_OFFSET 0x700
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+#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
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+#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
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+
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static struct pci_ops dw_pcie_ops;
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static struct pci_ops dw_pcie_ops;
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int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
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int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
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@@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_port *pp)
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int dw_pcie_link_up(struct pcie_port *pp)
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int dw_pcie_link_up(struct pcie_port *pp)
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{
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{
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+ u32 val;
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+
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if (pp->ops->link_up)
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if (pp->ops->link_up)
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return pp->ops->link_up(pp);
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return pp->ops->link_up(pp);
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- return 0;
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+ val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
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+ return val & PCIE_PHY_DEBUG_R1_LINK_UP;
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}
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}
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static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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