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@@ -39,7 +39,6 @@
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#define PIODATA_ENDIAN_SHIFT 6
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#define PIODATA_ENDIAN_SHIFT 6
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#define ENDIAN_SWAP_NONE 0
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#define ENDIAN_SWAP_NONE 0
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#define ENDIAN_SWAP_FULL 2
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#define ENDIAN_SWAP_FULL 2
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- #define OVERRIDE_HWINIT BIT(16)
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#define SATA_TOP_CTRL_TP_CTRL 0x8
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#define SATA_TOP_CTRL_TP_CTRL 0x8
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#define SATA_TOP_CTRL_PHY_CTRL 0xc
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#define SATA_TOP_CTRL_PHY_CTRL 0xc
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#define SATA_TOP_CTRL_PHY_CTRL_1 0x0
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#define SATA_TOP_CTRL_PHY_CTRL_1 0x0
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@@ -126,17 +125,13 @@ static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
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static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
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static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
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{
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{
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struct brcm_ahci_priv *priv = hpriv->plat_data;
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struct brcm_ahci_priv *priv = hpriv->plat_data;
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- u32 bus_ctrl, port_ctrl, host_caps;
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+ u32 port_ctrl, host_caps;
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int i;
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int i;
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/* Enable support for ALPM */
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/* Enable support for ALPM */
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- bus_ctrl = brcm_sata_readreg(priv->top_ctrl +
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- SATA_TOP_CTRL_BUS_CTRL);
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- brcm_sata_writereg(bus_ctrl | OVERRIDE_HWINIT,
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- priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
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host_caps = readl(hpriv->mmio + HOST_CAP);
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host_caps = readl(hpriv->mmio + HOST_CAP);
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- writel(host_caps | HOST_CAP_ALPM, hpriv->mmio);
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- brcm_sata_writereg(bus_ctrl, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
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+ if (!(host_caps & HOST_CAP_ALPM))
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+ hpriv->flags |= AHCI_HFLAG_YES_ALPM;
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/*
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/*
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* Adjust timeout to allow PLL sufficient time to lock while waking
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* Adjust timeout to allow PLL sufficient time to lock while waking
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@@ -360,6 +355,7 @@ static int brcm_ahci_probe(struct platform_device *pdev)
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if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
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if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
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hpriv->flags |= AHCI_HFLAG_NO_NCQ;
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hpriv->flags |= AHCI_HFLAG_NO_NCQ;
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+ hpriv->flags |= AHCI_HFLAG_NO_WRITE_TO_RO;
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ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
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ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
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&ahci_platform_sht);
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&ahci_platform_sht);
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