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@@ -23,33 +23,11 @@
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#ifndef CIK_REGS_H
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#define CIK_REGS_H
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-#define IH_VMID_0_LUT 0x3D40u
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-
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-#define BIF_DOORBELL_CNTL 0x530Cu
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-
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-#define SRBM_GFX_CNTL 0xE44
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-#define PIPEID(x) ((x) << 0)
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-#define MEID(x) ((x) << 2)
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-#define VMID(x) ((x) << 4)
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-#define QUEUEID(x) ((x) << 8)
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-
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-#define SQ_CONFIG 0x8C00
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-
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-#define SH_MEM_BASES 0x8C28
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/* if PTR32, these are the bases for scratch and lds */
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#define PRIVATE_BASE(x) ((x) << 0) /* scratch */
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#define SHARED_BASE(x) ((x) << 16) /* LDS */
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-#define SH_MEM_APE1_BASE 0x8C2C
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-/* if PTR32, this is the base location of GPUVM */
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-#define SH_MEM_APE1_LIMIT 0x8C30
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-/* if PTR32, this is the upper limit of GPUVM */
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-#define SH_MEM_CONFIG 0x8C34
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#define PTR32 (1 << 0)
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-#define PRIVATE_ATC (1 << 1)
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#define ALIGNMENT_MODE(x) ((x) << 2)
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-#define SH_MEM_ALIGNMENT_MODE_DWORD 0
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-#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
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-#define SH_MEM_ALIGNMENT_MODE_STRICT 2
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#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
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#define DEFAULT_MTYPE(x) ((x) << 4)
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#define APE1_MTYPE(x) ((x) << 7)
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@@ -58,137 +36,34 @@
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#define MTYPE_CACHED 0
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#define MTYPE_NONCACHED 3
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-
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-#define SH_STATIC_MEM_CONFIG 0x9604u
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-
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-#define TC_CFG_L1_LOAD_POLICY0 0xAC68
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-#define TC_CFG_L1_LOAD_POLICY1 0xAC6C
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-#define TC_CFG_L1_STORE_POLICY 0xAC70
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-#define TC_CFG_L2_LOAD_POLICY0 0xAC74
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-#define TC_CFG_L2_LOAD_POLICY1 0xAC78
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-#define TC_CFG_L2_STORE_POLICY0 0xAC7C
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-#define TC_CFG_L2_STORE_POLICY1 0xAC80
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-#define TC_CFG_L2_ATOMIC_POLICY 0xAC84
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-#define TC_CFG_L1_VOLATILE 0xAC88
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-#define TC_CFG_L2_VOLATILE 0xAC8C
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-
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-#define CP_PQ_WPTR_POLL_CNTL 0xC20C
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-#define WPTR_POLL_EN (1 << 31)
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-
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-#define CPC_INT_CNTL 0xC2D0
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-#define CP_ME1_PIPE0_INT_CNTL 0xC214
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-#define CP_ME1_PIPE1_INT_CNTL 0xC218
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-#define CP_ME1_PIPE2_INT_CNTL 0xC21C
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-#define CP_ME1_PIPE3_INT_CNTL 0xC220
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-#define CP_ME2_PIPE0_INT_CNTL 0xC224
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-#define CP_ME2_PIPE1_INT_CNTL 0xC228
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-#define CP_ME2_PIPE2_INT_CNTL 0xC22C
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-#define CP_ME2_PIPE3_INT_CNTL 0xC230
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-#define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
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-#define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
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-#define PRIV_REG_INT_ENABLE (1 << 23)
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-#define TIME_STAMP_INT_ENABLE (1 << 26)
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-#define GENERIC2_INT_ENABLE (1 << 29)
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-#define GENERIC1_INT_ENABLE (1 << 30)
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-#define GENERIC0_INT_ENABLE (1 << 31)
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-#define CP_ME1_PIPE0_INT_STATUS 0xC214
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-#define CP_ME1_PIPE1_INT_STATUS 0xC218
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-#define CP_ME1_PIPE2_INT_STATUS 0xC21C
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-#define CP_ME1_PIPE3_INT_STATUS 0xC220
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-#define CP_ME2_PIPE0_INT_STATUS 0xC224
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-#define CP_ME2_PIPE1_INT_STATUS 0xC228
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-#define CP_ME2_PIPE2_INT_STATUS 0xC22C
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-#define CP_ME2_PIPE3_INT_STATUS 0xC230
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-#define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
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-#define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
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-#define PRIV_REG_INT_STATUS (1 << 23)
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-#define TIME_STAMP_INT_STATUS (1 << 26)
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-#define GENERIC2_INT_STATUS (1 << 29)
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-#define GENERIC1_INT_STATUS (1 << 30)
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-#define GENERIC0_INT_STATUS (1 << 31)
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-
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-#define CP_HPD_EOP_BASE_ADDR 0xC904
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-#define CP_HPD_EOP_BASE_ADDR_HI 0xC908
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-#define CP_HPD_EOP_VMID 0xC90C
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-#define CP_HPD_EOP_CONTROL 0xC910
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-#define EOP_SIZE(x) ((x) << 0)
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-#define EOP_SIZE_MASK (0x3f << 0)
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-#define CP_MQD_BASE_ADDR 0xC914
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-#define CP_MQD_BASE_ADDR_HI 0xC918
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-#define CP_HQD_ACTIVE 0xC91C
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-#define CP_HQD_VMID 0xC920
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-
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-#define CP_HQD_PERSISTENT_STATE 0xC924u
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#define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8)
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#define PRELOAD_REQ (1 << 0)
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-#define CP_HQD_PIPE_PRIORITY 0xC928u
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-#define CP_HQD_QUEUE_PRIORITY 0xC92Cu
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-#define CP_HQD_QUANTUM 0xC930u
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+#define MQD_CONTROL_PRIV_STATE_EN (1U << 8)
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+
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+#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)
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+
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+#define IB_ATC_EN (1U << 23)
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+
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#define QUANTUM_EN 1U
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#define QUANTUM_SCALE_1MS (1U << 4)
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#define QUANTUM_DURATION(x) ((x) << 8)
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-#define CP_HQD_PQ_BASE 0xC934
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-#define CP_HQD_PQ_BASE_HI 0xC938
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-#define CP_HQD_PQ_RPTR 0xC93C
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-#define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
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-#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
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-#define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
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-#define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
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-#define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
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-#define DOORBELL_OFFSET(x) ((x) << 2)
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-#define DOORBELL_OFFSET_MASK (0x1fffff << 2)
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-#define DOORBELL_SOURCE (1 << 28)
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-#define DOORBELL_SCHD_HIT (1 << 29)
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-#define DOORBELL_EN (1 << 30)
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-#define DOORBELL_HIT (1 << 31)
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-#define CP_HQD_PQ_WPTR 0xC954
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-#define CP_HQD_PQ_CONTROL 0xC958
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-#define QUEUE_SIZE(x) ((x) << 0)
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-#define QUEUE_SIZE_MASK (0x3f << 0)
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#define RPTR_BLOCK_SIZE(x) ((x) << 8)
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-#define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
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#define MIN_AVAIL_SIZE(x) ((x) << 20)
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-#define PQ_ATC_EN (1 << 23)
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-#define PQ_VOLATILE (1 << 26)
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-#define NO_UPDATE_RPTR (1 << 27)
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-#define UNORD_DISPATCH (1 << 28)
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-#define ROQ_PQ_IB_FLIP (1 << 29)
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-#define PRIV_STATE (1 << 30)
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-#define KMD_QUEUE (1 << 31)
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-
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#define DEFAULT_RPTR_BLOCK_SIZE RPTR_BLOCK_SIZE(5)
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#define DEFAULT_MIN_AVAIL_SIZE MIN_AVAIL_SIZE(3)
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-#define CP_HQD_IB_BASE_ADDR 0xC95Cu
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-#define CP_HQD_IB_BASE_ADDR_HI 0xC960u
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-#define CP_HQD_IB_RPTR 0xC964u
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-#define CP_HQD_IB_CONTROL 0xC968u
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-#define IB_ATC_EN (1U << 23)
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-#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)
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-
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-#define AQL_ENABLE 1
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-
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-#define CP_HQD_DEQUEUE_REQUEST 0xC974
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-#define DEQUEUE_REQUEST_DRAIN 1
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-#define DEQUEUE_REQUEST_RESET 2
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-#define DEQUEUE_INT (1U << 8)
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+#define PQ_ATC_EN (1 << 23)
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+#define NO_UPDATE_RPTR (1 << 27)
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-#define CP_HQD_SEMA_CMD 0xC97Cu
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-#define CP_HQD_MSG_TYPE 0xC980u
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-#define CP_HQD_ATOMIC0_PREOP_LO 0xC984u
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-#define CP_HQD_ATOMIC0_PREOP_HI 0xC988u
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-#define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu
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-#define CP_HQD_ATOMIC1_PREOP_HI 0xC990u
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-#define CP_HQD_HQ_SCHEDULER0 0xC994u
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-#define CP_HQD_HQ_SCHEDULER1 0xC998u
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+#define DOORBELL_OFFSET(x) ((x) << 2)
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+#define DOORBELL_EN (1 << 30)
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+#define PRIV_STATE (1 << 30)
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+#define KMD_QUEUE (1 << 31)
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-#define CP_MQD_CONTROL 0xC99C
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-#define MQD_VMID(x) ((x) << 0)
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-#define MQD_VMID_MASK (0xf << 0)
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-#define MQD_CONTROL_PRIV_STATE_EN (1U << 8)
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+#define AQL_ENABLE 1
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#define SDMA_RB_VMID(x) (x << 24)
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#define SDMA_RB_ENABLE (1 << 0)
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@@ -202,33 +77,7 @@
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#define SDMA_VA_SHARED_BASE(x) (x << 8)
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#define GRBM_GFX_INDEX 0x30800
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-#define INSTANCE_INDEX(x) ((x) << 0)
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-#define SH_INDEX(x) ((x) << 8)
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-#define SE_INDEX(x) ((x) << 16)
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-#define SH_BROADCAST_WRITES (1 << 29)
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-#define INSTANCE_BROADCAST_WRITES (1 << 30)
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-#define SE_BROADCAST_WRITES (1 << 31)
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-
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-#define SQC_CACHES 0x30d20
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-#define SQC_POLICY 0x8C38u
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-#define SQC_VOLATILE 0x8C3Cu
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-#define CP_PERFMON_CNTL 0x36020
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-
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-#define ATC_VMID0_PASID_MAPPING 0x339Cu
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-#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u
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#define ATC_VMID_PASID_MAPPING_VALID (1U << 31)
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-#define ATC_VM_APERTURE0_CNTL 0x3310u
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-#define ATS_ACCESS_MODE_NEVER 0
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-#define ATS_ACCESS_MODE_ALWAYS 1
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-
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-#define ATC_VM_APERTURE0_CNTL2 0x3318u
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-#define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u
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-#define ATC_VM_APERTURE0_LOW_ADDR 0x3300u
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-#define ATC_VM_APERTURE1_CNTL 0x3314u
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-#define ATC_VM_APERTURE1_CNTL2 0x331Cu
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-#define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu
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-#define ATC_VM_APERTURE1_LOW_ADDR 0x3304u
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-
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#endif
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Oded Gabbay