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@@ -4,9 +4,9 @@
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#include "ddk750_power.h"
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#include "ddk750_dvi.h"
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-#define primaryWaitVerticalSync(delay) waitNextVerticalSync(0,delay)
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+#define primaryWaitVerticalSync(delay) waitNextVerticalSync(0, delay)
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-static void setDisplayControl(int ctrl,int dispState)
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+static void setDisplayControl(int ctrl, int dispState)
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{
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/* state != 0 means turn on both timing & plane en_bit */
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unsigned long ulDisplayCtrlReg, ulReservedBits;
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@@ -51,7 +51,7 @@ static void setDisplayControl(int ctrl,int dispState)
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POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
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} while((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) !=
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(ulDisplayCtrlReg & ~ulReservedBits));
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- printk("Set Panel Plane enbit:after tried %d times\n",cnt);
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+ printk("Set Panel Plane enbit:after tried %d times\n", cnt);
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}
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else
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{
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@@ -106,7 +106,7 @@ static void setDisplayControl(int ctrl,int dispState)
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POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
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} while((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) !=
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(ulDisplayCtrlReg & ~ulReservedBits));
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- printk("Set Crt Plane enbit:after tried %d times\n",cnt);
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+ printk("Set Crt Plane enbit:after tried %d times\n", cnt);
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}
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else
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{
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@@ -129,7 +129,7 @@ static void setDisplayControl(int ctrl,int dispState)
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}
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-static void waitNextVerticalSync(int ctrl,int delay)
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+static void waitNextVerticalSync(int ctrl, int delay)
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{
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unsigned int status;
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if(!ctrl){
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@@ -201,31 +201,31 @@ static void waitNextVerticalSync(int ctrl,int delay)
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}
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}
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-static void swPanelPowerSequence(int disp,int delay)
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+static void swPanelPowerSequence(int disp, int delay)
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{
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unsigned int reg;
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/* disp should be 1 to open sequence */
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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- reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,FPEN,disp);
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- POKE32(PANEL_DISPLAY_CTRL,reg);
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+ reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp);
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+ POKE32(PANEL_DISPLAY_CTRL, reg);
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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- reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,DATA,disp);
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- POKE32(PANEL_DISPLAY_CTRL,reg);
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+ reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, DATA, disp);
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+ POKE32(PANEL_DISPLAY_CTRL, reg);
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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- reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,VBIASEN,disp);
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- POKE32(PANEL_DISPLAY_CTRL,reg);
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+ reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, VBIASEN, disp);
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+ POKE32(PANEL_DISPLAY_CTRL, reg);
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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- reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,FPEN,disp);
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- POKE32(PANEL_DISPLAY_CTRL,reg);
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+ reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp);
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+ POKE32(PANEL_DISPLAY_CTRL, reg);
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primaryWaitVerticalSync(delay);
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}
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@@ -236,33 +236,33 @@ void ddk750_setLogicalDispOut(disp_output_t output)
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if(output & PNL_2_USAGE){
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/* set panel path controller select */
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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- reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,SELECT,(output & PNL_2_MASK)>>PNL_2_OFFSET);
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- POKE32(PANEL_DISPLAY_CTRL,reg);
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+ reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, SELECT, (output & PNL_2_MASK)>>PNL_2_OFFSET);
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+ POKE32(PANEL_DISPLAY_CTRL, reg);
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}
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if(output & CRT_2_USAGE){
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/* set crt path controller select */
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reg = PEEK32(CRT_DISPLAY_CTRL);
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- reg = FIELD_VALUE(reg,CRT_DISPLAY_CTRL,SELECT,(output & CRT_2_MASK)>>CRT_2_OFFSET);
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+ reg = FIELD_VALUE(reg, CRT_DISPLAY_CTRL, SELECT, (output & CRT_2_MASK)>>CRT_2_OFFSET);
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/*se blank off */
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- reg = FIELD_SET(reg,CRT_DISPLAY_CTRL,BLANK,OFF);
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- POKE32(CRT_DISPLAY_CTRL,reg);
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+ reg = FIELD_SET(reg, CRT_DISPLAY_CTRL, BLANK, OFF);
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+ POKE32(CRT_DISPLAY_CTRL, reg);
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}
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if(output & PRI_TP_USAGE){
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/* set primary timing and plane en_bit */
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- setDisplayControl(0,(output&PRI_TP_MASK)>>PRI_TP_OFFSET);
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+ setDisplayControl(0, (output&PRI_TP_MASK)>>PRI_TP_OFFSET);
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}
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if(output & SEC_TP_USAGE){
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/* set secondary timing and plane en_bit*/
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- setDisplayControl(1,(output&SEC_TP_MASK)>>SEC_TP_OFFSET);
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+ setDisplayControl(1, (output&SEC_TP_MASK)>>SEC_TP_OFFSET);
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}
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if(output & PNL_SEQ_USAGE){
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/* set panel sequence */
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- swPanelPowerSequence((output&PNL_SEQ_MASK)>>PNL_SEQ_OFFSET,4);
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+ swPanelPowerSequence((output&PNL_SEQ_MASK)>>PNL_SEQ_OFFSET, 4);
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}
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if(output & DAC_USAGE)
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