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@@ -6229,6 +6229,17 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
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I915_WRITE(CACHE_MODE_1,
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I915_WRITE(CACHE_MODE_1,
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_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
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_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
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+ /*
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+ * BSpec recommends 8x4 when MSAA is used,
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+ * however in practice 16x4 seems fastest.
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+ *
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+ * Note that PS/WM thread counts depend on the WIZ hashing
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+ * disable bit, which we don't touch here, but it's good
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+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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+ */
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+ I915_WRITE(GEN7_GT_MODE,
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+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
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+
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/*
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/*
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* WaIncreaseL3CreditsForVLVB0:vlv
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* WaIncreaseL3CreditsForVLVB0:vlv
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* This is the hardware default actually.
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* This is the hardware default actually.
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