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@@ -324,6 +324,63 @@ static const struct sun4i_hdmi_variant sun5i_variant = {
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.ddc_fifo_has_dir = true,
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};
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+static const struct sun4i_hdmi_variant sun6i_variant = {
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+ .has_ddc_parent_clk = true,
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+ .has_reset_control = true,
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+ .pad_ctrl0_init_val = 0xff |
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+ SUN4I_HDMI_PAD_CTRL0_TXEN |
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+ SUN4I_HDMI_PAD_CTRL0_CKEN |
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+ SUN4I_HDMI_PAD_CTRL0_PWENG |
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+ SUN4I_HDMI_PAD_CTRL0_PWEND |
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+ SUN4I_HDMI_PAD_CTRL0_PWENC |
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+ SUN4I_HDMI_PAD_CTRL0_LDODEN |
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+ SUN4I_HDMI_PAD_CTRL0_LDOCEN,
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+ .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
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+ SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
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+ SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
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+ SUN4I_HDMI_PAD_CTRL1_REG_DEN |
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+ SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
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+ SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
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+ SUN4I_HDMI_PAD_CTRL1_PWSDT |
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+ SUN4I_HDMI_PAD_CTRL1_PWSCK |
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+ SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
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+ SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
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+ SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
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+ .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
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+ SUN4I_HDMI_PLL_CTRL_CS(3) |
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+ SUN4I_HDMI_PLL_CTRL_CP_S(10) |
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+ SUN4I_HDMI_PLL_CTRL_S(4) |
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+ SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
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+ SUN4I_HDMI_PLL_CTRL_SDIV2 |
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+ SUN4I_HDMI_PLL_CTRL_LDO2_EN |
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+ SUN4I_HDMI_PLL_CTRL_LDO1_EN |
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+ SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
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+ SUN4I_HDMI_PLL_CTRL_PLL_EN,
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+
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+ .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
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+ .ddc_clk_pre_divider = 1,
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+ .ddc_clk_m_offset = 2,
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+
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+ .tmds_clk_div_offset = 1,
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+
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+ .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
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+ .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
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+ .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
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+ .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
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+ .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
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+ .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
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+ .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
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+ .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
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+ .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
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+ .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
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+ .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
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+ .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
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+ .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
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+
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+ .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG,
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+ .ddc_fifo_thres_incl = true,
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+};
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+
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static const struct regmap_config sun4i_hdmi_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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@@ -551,6 +608,7 @@ static int sun4i_hdmi_remove(struct platform_device *pdev)
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static const struct of_device_id sun4i_hdmi_of_table[] = {
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{ .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
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+ { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
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