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@@ -2820,6 +2820,74 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
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SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
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};
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+static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
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+ SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
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+ SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL2,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL3,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL4,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL5,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL6,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL7,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL8,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
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+ /* Hole */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM0,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out")),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM1,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out")),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM2,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x3, "1wire")),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM3,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out")),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM4,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out")),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM5,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out")),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM6,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out")),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM7,
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
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+};
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+
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static const struct sunxi_desc_pin sun7i_a20_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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@@ -3855,6 +3923,12 @@ static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
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.npins = ARRAY_SIZE(sun6i_a31_pins),
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};
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+static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
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+ .pins = sun6i_a31_r_pins,
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+ .npins = ARRAY_SIZE(sun6i_a31_r_pins),
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+ .pin_base = PL_BASE,
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+};
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+
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static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
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.pins = sun7i_a20_pins,
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.npins = ARRAY_SIZE(sun7i_a20_pins),
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