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@@ -247,9 +247,9 @@ static struct dw_spi_dma_ops mid_dma_ops = {
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/* Some specific info for SPI0 controller on Intel MID */
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-/* HW info for MRST CLk Control Unit, one 32b reg */
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+/* HW info for MRST Clk Control Unit, 32b reg per controller */
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#define MRST_SPI_CLK_BASE 100000000 /* 100m */
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-#define MRST_CLK_SPI0_REG 0xff11d86c
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+#define MRST_CLK_SPI_REG 0xff11d86c
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#define CLK_SPI_BDIV_OFFSET 0
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#define CLK_SPI_BDIV_MASK 0x00000007
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#define CLK_SPI_CDIV_OFFSET 9
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@@ -261,13 +261,16 @@ int dw_spi_mid_init(struct dw_spi *dws)
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void __iomem *clk_reg;
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u32 clk_cdiv;
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- clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
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+ clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
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if (!clk_reg)
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return -ENOMEM;
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- /* get SPI controller operating freq info */
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- clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
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+ /* Get SPI controller operating freq info */
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+ clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
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+ clk_cdiv &= CLK_SPI_CDIV_MASK;
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+ clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
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dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
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+
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iounmap(clk_reg);
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#ifdef CONFIG_SPI_DW_MID_DMA
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