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@@ -279,11 +279,18 @@
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll3",
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- "lb", "qspi", "z", "adsp";
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+ "lb", "qspi", "z";
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#power-domain-cells = <0>;
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};
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/* Fixed factor clocks */
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+ pll1_div2_clk: pll1_div2 {
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+ compatible = "fixed-factor-clock";
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+ clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
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+ #clock-cells = <0>;
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+ clock-div = <2>;
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+ clock-mult = <1>;
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+ };
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zs_clk: zs {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
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