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@@ -130,6 +130,42 @@ do { \
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#define smp_mb__before_spinlock() smp_wmb()
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#endif
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+/*
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+ * This barrier must provide two things:
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+ *
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+ * - it must guarantee a STORE before the spin_lock() is ordered against a
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+ * LOAD after it, see the comments at its two usage sites.
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+ *
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+ * - it must ensure the critical section is RCsc.
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+ *
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+ * The latter is important for cases where we observe values written by other
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+ * CPUs in spin-loops, without barriers, while being subject to scheduling.
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+ *
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+ * CPU0 CPU1 CPU2
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+ *
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+ * for (;;) {
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+ * if (READ_ONCE(X))
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+ * break;
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+ * }
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+ * X=1
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+ * <sched-out>
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+ * <sched-in>
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+ * r = X;
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+ *
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+ * without transitivity it could be that CPU1 observes X!=0 breaks the loop,
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+ * we get migrated and CPU2 sees X==0.
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+ *
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+ * Since most load-store architectures implement ACQUIRE with an smp_mb() after
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+ * the LL/SC loop, they need no further barriers. Similarly all our TSO
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+ * architectures imply an smp_mb() for each atomic instruction and equally don't
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+ * need more.
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+ *
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+ * Architectures that can implement ACQUIRE better need to take care.
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+ */
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+#ifndef smp_mb__after_spinlock
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+#define smp_mb__after_spinlock() do { } while (0)
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+#endif
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+
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/**
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* raw_spin_unlock_wait - wait until the spinlock gets unlocked
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* @lock: the spinlock in question.
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