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@@ -1814,6 +1814,68 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
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memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
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}
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+/*
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+ * Baseband Watchdog signatures:
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+ *
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+ * 0x04000539: BB hang when operating in HT40 DFS Channel.
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+ * Full chip reset is not required, but a recovery
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+ * mechanism is needed.
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+ *
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+ * 0x1300000a: Related to CAC deafness.
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+ * Chip reset is not required.
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+ *
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+ * 0x0400000a: Related to CAC deafness.
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+ * Full chip reset is required.
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+ *
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+ * 0x04000b09: RX state machine gets into an illegal state
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+ * when a packet with unsupported rate is received.
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+ * Full chip reset is required and PHY_RESTART has
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+ * to be disabled.
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+ *
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+ * 0x04000409: Packet stuck on receive.
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+ * Full chip reset is required for all chips except AR9340.
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+ */
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+
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+/*
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+ * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
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+ */
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+bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
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+{
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+ u32 val;
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+
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+ switch(ah->bb_watchdog_last_status) {
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+ case 0x04000539:
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+ val = REG_READ(ah, AR_PHY_RADAR_0);
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+ val &= (~AR_PHY_RADAR_0_FIRPWR);
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+ val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
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+ REG_WRITE(ah, AR_PHY_RADAR_0, val);
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+ udelay(1);
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+ val = REG_READ(ah, AR_PHY_RADAR_0);
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+ val &= ~AR_PHY_RADAR_0_FIRPWR;
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+ val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
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+ REG_WRITE(ah, AR_PHY_RADAR_0, val);
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+
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+ return false;
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+ case 0x1300000a:
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+ return false;
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+ case 0x0400000a:
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+ case 0x04000b09:
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+ return true;
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+ case 0x04000409:
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+ if (AR_SREV_9340(ah))
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+ return false;
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+ else
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+ return true;
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+ default:
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+ /*
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+ * For any other unknown signatures, do a
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+ * full chip reset.
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+ */
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+ return true;
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+ }
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+}
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+EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
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+
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void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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