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@@ -4040,6 +4040,7 @@ static void cim_intr_handler(struct adapter *adapter)
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{ MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
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{ TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
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{ TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
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+ { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
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{ 0 }
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};
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static const struct intr_info cim_upintr_info[] = {
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@@ -4074,11 +4075,27 @@ static void cim_intr_handler(struct adapter *adapter)
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{ 0 }
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};
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+ u32 val, fw_err;
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int fat;
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- if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
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+ fw_err = t4_read_reg(adapter, PCIE_FW_A);
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+ if (fw_err & PCIE_FW_ERR_F)
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t4_report_fw_error(adapter);
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+ /* When the Firmware detects an internal error which normally
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+ * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
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+ * in order to make sure the Host sees the Firmware Crash. So
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+ * if we have a Timer0 interrupt and don't see a Firmware Crash,
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+ * ignore the Timer0 interrupt.
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+ */
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+
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+ val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
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+ if (val & TIMER0INT_F)
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+ if (!(fw_err & PCIE_FW_ERR_F) ||
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+ (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
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+ t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
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+ TIMER0INT_F);
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+
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fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
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cim_intr_info) +
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t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
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