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@@ -4624,11 +4624,15 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
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yesno(intel_dp_source_supports_hbr2(intel_dp)),
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yesno(intel_dp_source_supports_hbr2(intel_dp)),
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yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
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yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
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- /* Set the max lane count for sink */
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- intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
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+ if (intel_dp->reset_link_params) {
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+ /* Set the max lane count for sink */
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+ intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
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- /* Set the max link BW for sink */
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- intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
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+ /* Set the max link BW for sink */
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+ intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
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+
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+ intel_dp->reset_link_params = false;
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+ }
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intel_dp_print_rates(intel_dp);
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intel_dp_print_rates(intel_dp);
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@@ -5010,6 +5014,8 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
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if (lspcon->active)
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if (lspcon->active)
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lspcon_resume(lspcon);
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lspcon_resume(lspcon);
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+ intel_dp->reset_link_params = true;
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+
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pps_lock(intel_dp);
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pps_lock(intel_dp);
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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@@ -5079,6 +5085,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
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long_hpd ? "long" : "short");
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long_hpd ? "long" : "short");
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if (long_hpd) {
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if (long_hpd) {
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+ intel_dp->reset_link_params = true;
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intel_dp->detect_done = false;
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intel_dp->detect_done = false;
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return IRQ_NONE;
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return IRQ_NONE;
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}
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}
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@@ -5947,6 +5954,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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intel_dig_port->max_lanes, port_name(port)))
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intel_dig_port->max_lanes, port_name(port)))
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return false;
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return false;
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+ intel_dp->reset_link_params = true;
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intel_dp->pps_pipe = INVALID_PIPE;
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intel_dp->pps_pipe = INVALID_PIPE;
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intel_dp->active_pipe = INVALID_PIPE;
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intel_dp->active_pipe = INVALID_PIPE;
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