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@@ -56,6 +56,19 @@
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#define PHYCTRL_DLLRDY_SHIFT 0x5
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#define PHYCTRL_DLLRDY_DONE 0x1
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#define PHYCTRL_DLLRDY_GOING 0x0
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+#define PHYCTRL_FREQSEL_200M 0x0
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+#define PHYCTRL_FREQSEL_50M 0x1
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+#define PHYCTRL_FREQSEL_100M 0x2
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+#define PHYCTRL_FREQSEL_150M 0x3
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+#define PHYCTRL_FREQSEL_MASK 0x3
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+#define PHYCTRL_FREQSEL_SHIFT 0xc
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+#define PHYCTRL_DR_MASK 0x7
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+#define PHYCTRL_DR_SHIFT 0x4
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+#define PHYCTRL_DR_50OHM 0x0
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+#define PHYCTRL_DR_33OHM 0x1
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+#define PHYCTRL_DR_66OHM 0x2
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+#define PHYCTRL_DR_100OHM 0x3
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+#define PHYCTRL_DR_40OHM 0x4
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struct rockchip_emmc_phy {
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unsigned int reg_offset;
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@@ -154,6 +167,20 @@ static int rockchip_emmc_phy_power_on(struct phy *phy)
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
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int ret = 0;
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+ /* DLL operation: 200 MHz */
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+ regmap_write(rk_phy->reg_base,
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+ rk_phy->reg_offset + GRF_EMMCPHY_CON0,
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+ HIWORD_UPDATE(PHYCTRL_FREQSEL_200M,
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+ PHYCTRL_FREQSEL_MASK,
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+ PHYCTRL_FREQSEL_SHIFT));
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+
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+ /* Drive impedance: 50 Ohm */
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+ regmap_write(rk_phy->reg_base,
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+ rk_phy->reg_offset + GRF_EMMCPHY_CON6,
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+ HIWORD_UPDATE(PHYCTRL_DR_50OHM,
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+ PHYCTRL_DR_MASK,
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+ PHYCTRL_DR_SHIFT));
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+
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/* Power up emmc phy analog blocks */
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ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
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if (ret)
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