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@@ -5012,6 +5012,8 @@ static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
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msr, MSR_TYPE_R | MSR_TYPE_W);
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}
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+#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
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+
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static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_only)
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{
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__vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
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@@ -6857,7 +6859,7 @@ static __init int hardware_setup(void)
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set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
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for (msr = 0x800; msr <= 0x8ff; msr++) {
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- if (msr == 0x839 /* TMCCT */)
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+ if (msr == X2APIC_MSR(APIC_TMCCT))
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continue;
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vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
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}
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@@ -6866,12 +6868,9 @@ static __init int hardware_setup(void)
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* TPR reads and writes can be virtualized even if virtual interrupt
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* delivery is not in use.
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*/
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- vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
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-
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- /* EOI */
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- vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
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- /* SELF-IPI */
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- vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
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+ vmx_disable_intercept_msr_x2apic(X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_R | MSR_TYPE_W, false);
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+ vmx_disable_intercept_msr_x2apic(X2APIC_MSR(APIC_EOI), MSR_TYPE_W, true);
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+ vmx_disable_intercept_msr_x2apic(X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W, true);
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if (enable_ept)
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vmx_enable_tdp();
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@@ -10041,17 +10040,17 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
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nested_vmx_disable_intercept_for_msr(
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msr_bitmap_l1, msr_bitmap_l0,
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- APIC_BASE_MSR + (APIC_TASKPRI >> 4),
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+ X2APIC_MSR(APIC_TASKPRI),
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MSR_TYPE_W);
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if (nested_cpu_has_vid(vmcs12)) {
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nested_vmx_disable_intercept_for_msr(
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msr_bitmap_l1, msr_bitmap_l0,
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- APIC_BASE_MSR + (APIC_EOI >> 4),
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+ X2APIC_MSR(APIC_EOI),
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MSR_TYPE_W);
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nested_vmx_disable_intercept_for_msr(
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msr_bitmap_l1, msr_bitmap_l0,
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- APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
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+ X2APIC_MSR(APIC_SELF_IPI),
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MSR_TYPE_W);
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}
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kunmap(page);
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