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@@ -644,8 +644,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
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}
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static void
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-intel_ddi_calculate_wrpll(int clock /* in Hz */,
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- unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
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+hsw_ddi_calculate_wrpll(int clock /* in Hz */,
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+ unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
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{
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uint64_t freq2k;
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unsigned p, n2, r2;
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@@ -709,14 +709,16 @@ intel_ddi_calculate_wrpll(int clock /* in Hz */,
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}
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static bool
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-hsw_ddi_pll_select(struct intel_crtc *intel_crtc, int output, int clock)
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+hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
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+ struct intel_encoder *intel_encoder,
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+ int clock)
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{
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- if (output == INTEL_OUTPUT_HDMI) {
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+ if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
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struct intel_shared_dpll *pll;
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uint32_t val;
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unsigned p, n2, r2;
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- intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
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+ hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
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val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
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WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
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@@ -749,12 +751,11 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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- int type = intel_encoder->type;
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int clock = intel_crtc->config.port_clock;
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intel_put_shared_dpll(intel_crtc);
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- return hsw_ddi_pll_select(intel_crtc, type, clock);
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+ return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
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}
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void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
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