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@@ -1,7 +1,7 @@
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/*
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* drivers/net/ethernet/mellanox/mlxsw/reg.h
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* Copyright (c) 2015 Mellanox Technologies. All rights reserved.
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- * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
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+ * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
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* Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
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* Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
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*
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@@ -386,7 +386,9 @@ enum mlxsw_reg_sfd_rec_action {
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/* forward and trap, trap_id is FDB_TRAP */
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MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
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/* trap and do not forward, trap_id is FDB_TRAP */
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- MLXSW_REG_SFD_REC_ACTION_TRAP = 3,
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+ MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
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+ /* forward to IP router */
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+ MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
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MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
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};
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@@ -3186,6 +3188,272 @@ static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
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mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
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}
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+/* RGCR - Router General Configuration Register
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+ * --------------------------------------------
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+ * The register is used for setting up the router configuration.
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+ */
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+#define MLXSW_REG_RGCR_ID 0x8001
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+#define MLXSW_REG_RGCR_LEN 0x28
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+
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+static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
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+ .id = MLXSW_REG_RGCR_ID,
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+ .len = MLXSW_REG_RGCR_LEN,
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+};
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+
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+/* reg_rgcr_ipv4_en
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+ * IPv4 router enable.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
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+
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+/* reg_rgcr_ipv6_en
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+ * IPv6 router enable.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
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+
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+/* reg_rgcr_max_router_interfaces
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+ * Defines the maximum number of active router interfaces for all virtual
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+ * routers.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
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+
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+/* reg_rgcr_usp
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+ * Update switch priority and packet color.
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+ * 0 - Preserve the value of Switch Priority and packet color.
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+ * 1 - Recalculate the value of Switch Priority and packet color.
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+ * Access: RW
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+ *
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+ * Note: Not supported by SwitchX and SwitchX-2.
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+ */
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+MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
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+
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+/* reg_rgcr_pcp_rw
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+ * Indicates how to handle the pcp_rewrite_en value:
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+ * 0 - Preserve the value of pcp_rewrite_en.
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+ * 2 - Disable PCP rewrite.
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+ * 3 - Enable PCP rewrite.
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+ * Access: RW
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+ *
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+ * Note: Not supported by SwitchX and SwitchX-2.
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+ */
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+MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
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+
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+/* reg_rgcr_activity_dis
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+ * Activity disable:
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+ * 0 - Activity will be set when an entry is hit (default).
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+ * 1 - Activity will not be set when an entry is hit.
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+ *
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+ * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
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+ * (RALUE).
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+ * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
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+ * Entry (RAUHT).
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+ * Bits 2:7 are reserved.
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+ * Access: RW
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+ *
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+ * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
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+ */
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+MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
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+
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+static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
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+{
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+ MLXSW_REG_ZERO(rgcr, payload);
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+ mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
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+}
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+
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+/* RITR - Router Interface Table Register
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+ * --------------------------------------
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+ * The register is used to configure the router interface table.
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+ */
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+#define MLXSW_REG_RITR_ID 0x8002
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+#define MLXSW_REG_RITR_LEN 0x40
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+
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+static const struct mlxsw_reg_info mlxsw_reg_ritr = {
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+ .id = MLXSW_REG_RITR_ID,
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+ .len = MLXSW_REG_RITR_LEN,
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+};
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+
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+/* reg_ritr_enable
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+ * Enables routing on the router interface.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
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+
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+/* reg_ritr_ipv4
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+ * IPv4 routing enable. Enables routing of IPv4 traffic on the router
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+ * interface.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
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+
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+/* reg_ritr_ipv6
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+ * IPv6 routing enable. Enables routing of IPv6 traffic on the router
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+ * interface.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
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+
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+enum mlxsw_reg_ritr_if_type {
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+ MLXSW_REG_RITR_VLAN_IF,
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+ MLXSW_REG_RITR_FID_IF,
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+ MLXSW_REG_RITR_SP_IF,
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+};
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+
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+/* reg_ritr_type
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+ * Router interface type.
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+ * 0 - VLAN interface.
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+ * 1 - FID interface.
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+ * 2 - Sub-port interface.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
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+
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+enum {
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+ MLXSW_REG_RITR_RIF_CREATE,
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+ MLXSW_REG_RITR_RIF_DEL,
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+};
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+
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+/* reg_ritr_op
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+ * Opcode:
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+ * 0 - Create or edit RIF.
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+ * 1 - Delete RIF.
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+ * Reserved for SwitchX-2. For Spectrum, editing of interface properties
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+ * is not supported. An interface must be deleted and re-created in order
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+ * to update properties.
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+ * Access: WO
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+ */
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+MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
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+
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+/* reg_ritr_rif
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+ * Router interface index. A pointer to the Router Interface Table.
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+ * Access: Index
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+ */
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+MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
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+
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+/* reg_ritr_ipv4_fe
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+ * IPv4 Forwarding Enable.
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+ * Enables routing of IPv4 traffic on the router interface. When disabled,
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+ * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
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+ * Not supported in SwitchX-2.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
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+
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+/* reg_ritr_ipv6_fe
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+ * IPv6 Forwarding Enable.
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+ * Enables routing of IPv6 traffic on the router interface. When disabled,
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+ * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
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+ * Not supported in SwitchX-2.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
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+
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+/* reg_ritr_virtual_router
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+ * Virtual router ID associated with the router interface.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
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+
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+/* reg_ritr_mtu
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+ * Router interface MTU.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
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+
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+/* reg_ritr_if_swid
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+ * Switch partition ID.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
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+
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+/* reg_ritr_if_mac
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+ * Router interface MAC address.
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+ * In Spectrum, all MAC addresses must have the same 38 MSBits.
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+ * Access: RW
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+ */
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+MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
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+
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+/* VLAN Interface */
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+
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+/* reg_ritr_vlan_if_vid
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+ * VLAN ID.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
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+
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+/* FID Interface */
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+
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+/* reg_ritr_fid_if_fid
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+ * Filtering ID. Used to connect a bridge to the router. Only FIDs from
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+ * the vFID range are supported.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
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+
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+static inline void mlxsw_reg_ritr_fid_set(char *payload,
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+ enum mlxsw_reg_ritr_if_type rif_type,
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+ u16 fid)
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+{
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+ if (rif_type == MLXSW_REG_RITR_FID_IF)
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+ mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
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+ else
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+ mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
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+}
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+
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+/* Sub-port Interface */
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+
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+/* reg_ritr_sp_if_lag
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+ * LAG indication. When this bit is set the system_port field holds the
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+ * LAG identifier.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
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+
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+/* reg_ritr_sp_system_port
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+ * Port unique indentifier. When lag bit is set, this field holds the
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+ * lag_id in bits 0:9.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
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+
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+/* reg_ritr_sp_if_vid
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+ * VLAN ID.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
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+
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+static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
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+{
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+ MLXSW_REG_ZERO(ritr, payload);
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+ mlxsw_reg_ritr_rif_set(payload, rif);
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+}
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+
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+static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
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+ u16 system_port, u16 vid)
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+{
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+ mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
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+ mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
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+ mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
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+}
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+
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+static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
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+ enum mlxsw_reg_ritr_if_type type,
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+ u16 rif, u16 mtu, const char *mac)
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+{
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+ bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
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+
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+ MLXSW_REG_ZERO(ritr, payload);
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+ mlxsw_reg_ritr_enable_set(payload, enable);
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+ mlxsw_reg_ritr_ipv4_set(payload, 1);
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+ mlxsw_reg_ritr_type_set(payload, type);
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+ mlxsw_reg_ritr_op_set(payload, op);
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+ mlxsw_reg_ritr_rif_set(payload, rif);
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+ mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
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+ mlxsw_reg_ritr_mtu_set(payload, mtu);
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+ mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
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+}
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+
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/* MFCR - Management Fan Control Register
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* --------------------------------------
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* This register controls the settings of the Fan Speed PWM mechanism.
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@@ -3924,6 +4192,10 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
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return "HTGT";
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case MLXSW_REG_HPKT_ID:
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return "HPKT";
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+ case MLXSW_REG_RGCR_ID:
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+ return "RGCR";
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+ case MLXSW_REG_RITR_ID:
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+ return "RITR";
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case MLXSW_REG_MFCR_ID:
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return "MFCR";
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case MLXSW_REG_MFSC_ID:
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