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@@ -1066,11 +1066,19 @@ static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
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if (!output)
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return -ENODEV;
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+ /*
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+ * The ->setup_clock() callback is optional, but if encoders don't
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+ * implement it they most likely need to do the equivalent within the
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+ * ->mode_fixup() callback.
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+ */
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+ if (!output->ops || !output->ops->setup_clock)
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+ return 0;
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+
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/*
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* This assumes that the parent clock is pll_d_out0 or pll_d2_out
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* respectively, each of which divides the base pll_d by 2.
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*/
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- err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
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+ err = output->ops->setup_clock(output, dc->clk, pclk, &div);
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if (err < 0) {
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dev_err(dc->dev, "failed to setup clock: %ld\n", err);
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return err;
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