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@@ -34,6 +34,8 @@
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#include "oss/oss_2_0_d.h"
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#include "oss/oss_2_0_d.h"
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#include "oss/oss_2_0_sh_mask.h"
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#include "oss/oss_2_0_sh_mask.h"
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+#include "bif/bif_4_1_d.h"
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+
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static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
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static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
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static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
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static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
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static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
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static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
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@@ -438,6 +440,32 @@ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
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amdgpu_ring_write(ring, 2);
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amdgpu_ring_write(ring, 2);
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}
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}
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+/**
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+ * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush
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+ *
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+ * @ring: amdgpu_ring pointer
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+ *
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+ * Emits an hdp flush.
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+ */
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+static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
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+{
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+ amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
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+ amdgpu_ring_write(ring, 0);
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+}
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+
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+/**
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+ * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate
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+ *
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+ * @ring: amdgpu_ring pointer
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+ *
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+ * Emits an hdp invalidate.
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+ */
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+static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
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+{
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+ amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
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+ amdgpu_ring_write(ring, 1);
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+}
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+
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/**
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/**
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* uvd_v4_2_ring_test_ring - register write test
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* uvd_v4_2_ring_test_ring - register write test
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*
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*
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@@ -763,6 +791,8 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
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.parse_cs = amdgpu_uvd_ring_parse_cs,
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.parse_cs = amdgpu_uvd_ring_parse_cs,
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.emit_ib = uvd_v4_2_ring_emit_ib,
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.emit_ib = uvd_v4_2_ring_emit_ib,
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.emit_fence = uvd_v4_2_ring_emit_fence,
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.emit_fence = uvd_v4_2_ring_emit_fence,
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+ .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush,
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+ .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate,
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.test_ring = uvd_v4_2_ring_test_ring,
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.test_ring = uvd_v4_2_ring_test_ring,
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.test_ib = uvd_v4_2_ring_test_ib,
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.test_ib = uvd_v4_2_ring_test_ib,
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.insert_nop = amdgpu_ring_insert_nop,
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.insert_nop = amdgpu_ring_insert_nop,
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