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@@ -1364,7 +1364,18 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
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ret = atmel_smc_cs_conf_set_timing(smcconf,
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ret = atmel_smc_cs_conf_set_timing(smcconf,
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ATMEL_HSMC_TIMINGS_TADL_SHIFT,
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ATMEL_HSMC_TIMINGS_TADL_SHIFT,
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ncycles);
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ncycles);
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- if (ret)
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+ /*
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+ * Version 4 of the ONFI spec mandates that tADL be at least 400
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+ * nanoseconds, but, depending on the master clock rate, 400 ns may not
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+ * fit in the tADL field of the SMC reg. We need to relax the check and
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+ * accept the -ERANGE return code.
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+ *
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+ * Note that previous versions of the ONFI spec had a lower tADL_min
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+ * (100 or 200 ns). It's not clear why this timing constraint got
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+ * increased but it seems most NANDs are fine with values lower than
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+ * 400ns, so we should be safe.
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+ */
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+ if (ret && ret != -ERANGE)
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return ret;
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return ret;
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
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