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@@ -3874,16 +3874,18 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
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((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
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}
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reg_table->last = i;
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- while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) &&
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+ while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
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(num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
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- t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
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+ t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
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+ >> MEM_ID_SHIFT);
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if (module_index == t_mem_id) {
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reg_table->mc_reg_table_entry[num_ranges].mclk_max =
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- (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT);
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+ (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
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+ >> CLOCK_RANGE_SHIFT);
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for (i = 0, j = 1; i < reg_table->last; i++) {
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if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
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reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
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- (u32)*((u32 *)reg_data + j);
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+ (u32)le32_to_cpu(*((u32 *)reg_data + j));
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j++;
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} else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
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reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
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@@ -3895,7 +3897,7 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
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reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
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((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
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}
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- if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK)
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+ if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
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return -EINVAL;
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reg_table->num_entries = num_ranges;
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} else
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