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@@ -6429,6 +6429,7 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
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unsigned features, pidx, sbufcnt;
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int ret, mtu;
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u32 sbufs, updthresh;
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+ resource_size_t vl15off;
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/* pport structs are contiguous, allocated after devdata */
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ppd = (struct qib_pportdata *)(dd + 1);
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@@ -6677,29 +6678,27 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
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qib_7322_config_ctxts(dd);
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qib_set_ctxtcnt(dd);
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- if (qib_wc_pat) {
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- resource_size_t vl15off;
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- /*
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- * We do not set WC on the VL15 buffers to avoid
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- * a rare problem with unaligned writes from
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- * interrupt-flushed store buffers, so we need
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- * to map those separately here. We can't solve
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- * this for the rarely used mtrr case.
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- */
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- ret = init_chip_wc_pat(dd, 0);
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- if (ret)
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- goto bail;
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+ /*
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+ * We do not set WC on the VL15 buffers to avoid
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+ * a rare problem with unaligned writes from
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+ * interrupt-flushed store buffers, so we need
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+ * to map those separately here. We can't solve
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+ * this for the rarely used mtrr case.
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+ */
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+ ret = init_chip_wc_pat(dd, 0);
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+ if (ret)
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+ goto bail;
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- /* vl15 buffers start just after the 4k buffers */
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- vl15off = dd->physaddr + (dd->piobufbase >> 32) +
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- dd->piobcnt4k * dd->align4k;
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- dd->piovl15base = ioremap_nocache(vl15off,
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- NUM_VL15_BUFS * dd->align4k);
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- if (!dd->piovl15base) {
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- ret = -ENOMEM;
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- goto bail;
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- }
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+ /* vl15 buffers start just after the 4k buffers */
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+ vl15off = dd->physaddr + (dd->piobufbase >> 32) +
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+ dd->piobcnt4k * dd->align4k;
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+ dd->piovl15base = ioremap_nocache(vl15off,
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+ NUM_VL15_BUFS * dd->align4k);
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+ if (!dd->piovl15base) {
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+ ret = -ENOMEM;
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+ goto bail;
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}
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+
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qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
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ret = 0;
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