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@@ -132,10 +132,13 @@
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#define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i))
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#define ASRCFG_NDPRi_SHIFT(i) (18 + i)
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#define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i))
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+#define ASRCFG_NDPRi_ALL_SHIFT 18
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+#define ASRCFG_NDPRi_ALL_MASK (7 << ASRCFG_NDPRi_ALL_SHIFT)
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#define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i))
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#define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2))
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#define ASRCFG_POSTMODi_WIDTH 2
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#define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
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+#define ASRCFG_POSTMODi_ALL_MASK (ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
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#define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
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#define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i))
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#define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i))
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@@ -143,6 +146,7 @@
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#define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2))
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#define ASRCFG_PREMODi_WIDTH 2
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#define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
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+#define ASRCFG_PREMODi_ALL_MASK (ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
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#define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
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#define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i))
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#define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i))
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@@ -434,6 +438,7 @@ struct fsl_asrc_pair {
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* @channel_avail: non-occupied channel numbers
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* @asrc_rate: default sample rate for ASoC Back-Ends
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* @asrc_width: default sample width for ASoC Back-Ends
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+ * @regcache_cfg: store register value of REG_ASRCFG
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*/
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struct fsl_asrc {
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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@@ -453,6 +458,8 @@ struct fsl_asrc {
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int asrc_rate;
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int asrc_width;
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+
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+ u32 regcache_cfg;
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};
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extern struct snd_soc_platform_driver fsl_asrc_platform;
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