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@@ -38,8 +38,23 @@ Optional properties:
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- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
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which includes IRQ mux selection register, and the offset of the IRQ mux
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selection register.
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+ - ngpios: Number of gpios in a bank (to use if bank gpio numbers is less
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+ than 16).
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+ - gpio-ranges: Define a dedicated mapping between a pin-controller and
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+ a gpio controller. Format is <&phandle a b c> with:
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+ -(phandle): phandle of pin-controller.
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+ -(a): gpio base offset in range.
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+ -(b): pin base offset in range.
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+ -(c): gpio count in range
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+ This entry has to be used either if there are holes inside a bank:
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+ GPIOB0/B1/B2/B14/B15 (see example 2)
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+ or if banks are not contiguous:
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+ GPIOA/B/C/E...
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+ NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
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+ have to use a "gpio-ranges" entry.
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+ More details in Documentation/devicetree/bindings/gpio/gpio.txt.
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-Example:
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+Example 1:
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#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
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...
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@@ -61,6 +76,43 @@ Example:
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pin-functions nodes follow...
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};
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+Example 2:
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+#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
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+...
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+
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+ pinctrl: pin-controller {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,stm32f429-pinctrl";
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+ ranges = <0 0x40020000 0x3000>;
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+ pins-are-numbered;
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+
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+ gpioa: gpio@40020000 {
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ reg = <0x0 0x400>;
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+ resets = <&reset_ahb1 0>;
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+ st,bank-name = "GPIOA";
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+ gpio-ranges = <&pinctrl 0 0 16>;
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+ };
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+
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+ gpiob: gpio@40020400 {
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ reg = <0x0 0x400>;
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+ resets = <&reset_ahb1 0>;
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+ st,bank-name = "GPIOB";
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+ ngpios = 4;
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+ gpio-ranges = <&pinctrl 0 16 3>,
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+ <&pinctrl 14 30 2>;
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+ };
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+
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+
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+ ...
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+ pin-functions nodes follow...
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+ };
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+
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+
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Contents of function subnode node:
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----------------------------------
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Subnode format
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