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@@ -680,17 +680,36 @@ int hidma_ll_setup(struct hidma_lldev *lldev)
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writel(HIDMA_EVRE_SIZE * nr_tres,
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writel(HIDMA_EVRE_SIZE * nr_tres,
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lldev->evca + HIDMA_EVCA_RING_LEN_REG);
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lldev->evca + HIDMA_EVCA_RING_LEN_REG);
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- /* support IRQ only for now */
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+ /* configure interrupts */
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+ hidma_ll_setup_irq(lldev, lldev->msi_support);
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+
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+ rc = hidma_ll_enable(lldev);
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+ if (rc)
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+ return rc;
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+
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+ return rc;
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+}
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+
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+void hidma_ll_setup_irq(struct hidma_lldev *lldev, bool msi)
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+{
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+ u32 val;
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+
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+ lldev->msi_support = msi;
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+
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+ /* disable interrupts again after reset */
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+ writel(0, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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+ writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
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+
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+ /* support IRQ by default */
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val = readl(lldev->evca + HIDMA_EVCA_INTCTRL_REG);
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val = readl(lldev->evca + HIDMA_EVCA_INTCTRL_REG);
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val &= ~0xF;
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val &= ~0xF;
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- val |= 0x1;
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+ if (!lldev->msi_support)
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+ val = val | 0x1;
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writel(val, lldev->evca + HIDMA_EVCA_INTCTRL_REG);
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writel(val, lldev->evca + HIDMA_EVCA_INTCTRL_REG);
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/* clear all pending interrupts and enable them */
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/* clear all pending interrupts and enable them */
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writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
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writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
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-
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- return hidma_ll_enable(lldev);
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}
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}
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struct hidma_lldev *hidma_ll_init(struct device *dev, u32 nr_tres,
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struct hidma_lldev *hidma_ll_init(struct device *dev, u32 nr_tres,
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