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@@ -488,26 +488,26 @@ static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
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gc->chip_types[0].handler = handle_level_irq;
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gc->chip_types[0].handler = handle_level_irq;
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gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS;
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gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS;
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gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN;
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gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN;
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- gc->chip_types[0].chip.irq_startup = gpio_startup_irq,
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- gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit,
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- gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit,
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- gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit,
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- gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type,
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- gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake,
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- gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND,
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+ gc->chip_types[0].chip.irq_startup = gpio_startup_irq;
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+ gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
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+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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+ gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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+ gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type;
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+ gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake;
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+ gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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/* edge chip type */
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/* edge chip type */
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gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types[1].handler = handle_edge_irq;
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gc->chip_types[1].handler = handle_edge_irq;
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gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS;
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gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS;
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gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN;
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gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN;
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- gc->chip_types[1].chip.irq_startup = gpio_startup_irq,
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- gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit,
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- gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit,
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- gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit,
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- gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type,
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- gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake,
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- gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND,
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+ gc->chip_types[1].chip.irq_startup = gpio_startup_irq;
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+ gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit;
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+ gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
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+ gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
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+ gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type;
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+ gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake;
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+ gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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/* Setup chained handler for this GPIO bank */
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/* Setup chained handler for this GPIO bank */
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irq_set_handler_data(bank->irq, bank);
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irq_set_handler_data(bank->irq, bank);
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