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@@ -32,6 +32,11 @@
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#define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
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#define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
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/* Controller needs 4x internal clock */
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/* Controller needs 4x internal clock */
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#define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
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#define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
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+/*
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+ * TKT253890, Controller needs driver to fill txfifo till 16 byte to
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+ * trigger data transfer even though extern data will not transferred.
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+ */
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+#define QUADSPI_QUIRK_TKT253890 (1 << 2)
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/* The registers */
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/* The registers */
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#define QUADSPI_MCR 0x00
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#define QUADSPI_MCR 0x00
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@@ -202,6 +207,7 @@
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enum fsl_qspi_devtype {
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enum fsl_qspi_devtype {
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FSL_QUADSPI_VYBRID,
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FSL_QUADSPI_VYBRID,
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FSL_QUADSPI_IMX6SX,
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FSL_QUADSPI_IMX6SX,
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+ FSL_QUADSPI_IMX7D,
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};
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};
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struct fsl_qspi_devtype_data {
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struct fsl_qspi_devtype_data {
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@@ -228,6 +234,15 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
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.driver_data = QUADSPI_QUIRK_4X_INT_CLK,
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.driver_data = QUADSPI_QUIRK_4X_INT_CLK,
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};
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};
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+static struct fsl_qspi_devtype_data imx7d_data = {
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+ .devtype = FSL_QUADSPI_IMX7D,
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+ .rxfifo = 512,
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+ .txfifo = 512,
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+ .ahb_buf_size = 1024,
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+ .driver_data = QUADSPI_QUIRK_TKT253890
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+ | QUADSPI_QUIRK_4X_INT_CLK,
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+};
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+
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#define FSL_QSPI_MAX_CHIP 4
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#define FSL_QSPI_MAX_CHIP 4
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struct fsl_qspi {
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struct fsl_qspi {
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struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
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struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
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@@ -259,6 +274,11 @@ static inline int needs_4x_clock(struct fsl_qspi *q)
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return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
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return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
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}
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}
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+static inline int needs_fill_txfifo(struct fsl_qspi *q)
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+{
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+ return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
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+}
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+
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/*
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/*
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* An IC bug makes us to re-arrange the 32-bit data.
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* An IC bug makes us to re-arrange the 32-bit data.
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* The following chips, such as IMX6SLX, have fixed this bug.
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* The following chips, such as IMX6SLX, have fixed this bug.
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@@ -560,6 +580,11 @@ static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
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txbuf++;
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txbuf++;
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}
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}
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+ /* fill the TXFIFO upto 16 bytes for i.MX7d */
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+ if (needs_fill_txfifo(q))
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+ for (; i < 4; i++)
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+ writel(tmp, q->iobase + QUADSPI_TBDR);
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+
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/* Trigger it */
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/* Trigger it */
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ret = fsl_qspi_runcmd(q, opcode, to, count);
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ret = fsl_qspi_runcmd(q, opcode, to, count);
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@@ -679,6 +704,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
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static const struct of_device_id fsl_qspi_dt_ids[] = {
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static const struct of_device_id fsl_qspi_dt_ids[] = {
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{ .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
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{ .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
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{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
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{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
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+ { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
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{ /* sentinel */ }
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{ /* sentinel */ }
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};
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};
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MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
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MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
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