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@@ -172,7 +172,7 @@ static void i8xx_destroy_pages(struct page *page)
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#define I810_GTT_ORDER 4
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static int i810_setup(void)
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{
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- u32 reg_addr;
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+ phys_addr_t reg_addr;
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char *gtt_table;
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/* i81x does not preallocate the gtt. It's always 64kb in size. */
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@@ -181,7 +181,7 @@ static int i810_setup(void)
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return -ENOMEM;
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intel_private.i81x_gtt_table = gtt_table;
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- reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR);
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+ reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
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intel_private.registers = ioremap(reg_addr, KB(64));
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if (!intel_private.registers)
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@@ -782,9 +782,9 @@ EXPORT_SYMBOL(intel_enable_gtt);
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static int i830_setup(void)
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{
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- u32 reg_addr;
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+ phys_addr_t reg_addr;
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- reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR);
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+ reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
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intel_private.registers = ioremap(reg_addr, KB(64));
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if (!intel_private.registers)
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@@ -1102,10 +1102,10 @@ static void i965_write_entry(dma_addr_t addr,
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static int i9xx_setup(void)
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{
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- u32 reg_addr;
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+ phys_addr_t reg_addr;
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int size = KB(512);
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- reg_addr = pci_bus_address(intel_private.pcidev, I915_MMADR_BAR);
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+ reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
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intel_private.registers = ioremap(reg_addr, size);
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if (!intel_private.registers)
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@@ -1114,7 +1114,7 @@ static int i9xx_setup(void)
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switch (INTEL_GTT_GEN) {
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case 3:
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intel_private.gtt_phys_addr =
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- pci_bus_address(intel_private.pcidev, I915_PTE_BAR);
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+ pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
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break;
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case 5:
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intel_private.gtt_phys_addr = reg_addr + MB(2);
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