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drm: bridge/dw_hdmi: add function dw_hdmi_phy_enable_spare

RK3288 HDMI will not work without the spare bit of
HDMI_PHY_CONF0 enable

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Andy Yan 10 years ago
parent
a4d3b8b050
commit
d346c14eee
2 changed files with 9 additions and 1 deletions
Split View Show Diff Stats
  1. 7 0
      drivers/gpu/drm/bridge/dw_hdmi.c
  2. 2 1
      drivers/gpu/drm/bridge/dw_hdmi.h

+ 7 - 0
drivers/gpu/drm/bridge/dw_hdmi.c
View File 

@@ -713,6 +713,13 @@ static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 
 			 HDMI_PHY_CONF0_ENTMDS_MASK);
 
 }
 
 
+static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 
+{
 
+	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 
+			 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 
+			 HDMI_PHY_CONF0_SPARECTRL_MASK);
 
+}
 
+
 
 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 
 {
 
 	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,

+ 2 - 1
drivers/gpu/drm/bridge/dw_hdmi.h
View File 

@@ -837,7 +837,8 @@ enum {
 
 	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
 
 	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
 
 	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
 
-	HDMI_PHY_CONF0_SPARECTRL = 0x20,
 
+	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
 
+	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
 
 	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
 
 	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
 
 	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,