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@@ -99,27 +99,27 @@ static int dnv_handle_irq(struct uart_port *p)
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struct uart_8250_port *up = up_to_u8250p(p);
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struct uart_8250_port *up = up_to_u8250p(p);
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unsigned int fisr = serial_port_in(p, INTEL_MID_UART_DNV_FISR);
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unsigned int fisr = serial_port_in(p, INTEL_MID_UART_DNV_FISR);
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u32 status;
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u32 status;
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- int ret = IRQ_NONE;
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+ int ret = 0;
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int err;
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int err;
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if (fisr & BIT(2)) {
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if (fisr & BIT(2)) {
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err = hsu_dma_get_status(&mid->dma_chip, 1, &status);
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err = hsu_dma_get_status(&mid->dma_chip, 1, &status);
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if (err > 0) {
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if (err > 0) {
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serial8250_rx_dma_flush(up);
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serial8250_rx_dma_flush(up);
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- ret |= IRQ_HANDLED;
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+ ret |= 1;
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} else if (err == 0)
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} else if (err == 0)
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ret |= hsu_dma_do_irq(&mid->dma_chip, 1, status);
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ret |= hsu_dma_do_irq(&mid->dma_chip, 1, status);
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}
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}
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if (fisr & BIT(1)) {
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if (fisr & BIT(1)) {
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err = hsu_dma_get_status(&mid->dma_chip, 0, &status);
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err = hsu_dma_get_status(&mid->dma_chip, 0, &status);
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if (err > 0)
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if (err > 0)
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- ret |= IRQ_HANDLED;
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+ ret |= 1;
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else if (err == 0)
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else if (err == 0)
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ret |= hsu_dma_do_irq(&mid->dma_chip, 0, status);
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ret |= hsu_dma_do_irq(&mid->dma_chip, 0, status);
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}
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}
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if (fisr & BIT(0))
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if (fisr & BIT(0))
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ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
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ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
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- return ret;
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+ return IRQ_RETVAL(ret);
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}
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}
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#define DNV_DMA_CHAN_OFFSET 0x80
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#define DNV_DMA_CHAN_OFFSET 0x80
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