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@@ -90,7 +90,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
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/* This magic is from the original code */
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/* This magic is from the original code */
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writel(0, reg_base + AHCI_RWCR);
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writel(0, reg_base + AHCI_RWCR);
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- mdelay(5);
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+ msleep(5);
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sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
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sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
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sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
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@@ -105,7 +105,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
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(0x7 << 20), (0x3 << 20));
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(0x7 << 20), (0x3 << 20));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
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sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
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(0x1f << 5), (0x19 << 5));
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(0x1f << 5), (0x19 << 5));
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- mdelay(5);
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+ msleep(5);
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sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
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sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
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@@ -137,7 +137,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
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udelay(1);
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udelay(1);
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} while (1);
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} while (1);
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- mdelay(15);
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+ msleep(15);
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writel(0x7, reg_base + AHCI_RWCR);
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writel(0x7, reg_base + AHCI_RWCR);
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