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@@ -4936,11 +4936,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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encoder->pre_enable(encoder);
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}
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- if (intel_crtc->config->has_pch_encoder) {
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- intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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- true);
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+ if (intel_crtc->config->has_pch_encoder)
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dev_priv->display.fdi_link_train(crtc);
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- }
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if (!is_dsi)
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intel_ddi_enable_pipe_clock(intel_crtc);
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@@ -4977,6 +4974,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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intel_opregion_notify_encoder(encoder, true);
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}
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+ if (intel_crtc->config->has_pch_encoder)
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+ intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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+ true);
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+
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/* If we change the relative order between pipe/planes enabling, we need
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* to change the workaround. */
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hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
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@@ -5061,6 +5062,10 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
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bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
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+ if (intel_crtc->config->has_pch_encoder)
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+ intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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+ false);
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+
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for_each_encoder_on_crtc(dev, crtc, encoder) {
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intel_opregion_notify_encoder(encoder, false);
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encoder->disable(encoder);
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@@ -5069,9 +5074,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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drm_crtc_vblank_off(crtc);
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assert_vblank_disabled(crtc);
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- if (intel_crtc->config->has_pch_encoder)
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- intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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- false);
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intel_disable_pipe(intel_crtc);
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if (intel_crtc->config->dp_encoder_is_mst)
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